Electrical Characteristics

Electrical Characteristics
(Limits are 100% tested at T_A = +25°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested. Specifications to the minimum and maximum operating temperature are guaranteed by design and are not production tested.)
PARAMETER	SYMBOL	CONDITIONS		MIN	TYP	MAX	UNITS
POWER SUPPLY
Voltage Low	V_L	IOB power rail when present		1.71		3.63	V
Supply Current for Voltage Low	I_VL				6	60	μA
IOA, IOB PINS: GENERAL DATA
1-Wire Pullup Voltage A	V_PUPA	IOA pin only	(Note 1)	1.71	3.3	3.63	V
1-Wire Pullup Resistance A	R_PUPA	IOA pin only	(Note 2)	300		1000	Ω
1-Wire Pullup Resistance B	R_PUPB	IOB pin only	(Note 2)	300		10000	Ω
Supply Capacitance	C_SUPPLY	IOA or V_L first powered (Note 3)			2		nF
Input Capacitance A	C_IOA	IOA pin only	(Note 3)		2		nF
Input Capacitance B	C_IOB	IOB pin only			15		pF
Input Load Current A	I_{L_IOA}	(Note 4)			10	100	uA
Input Load Current B	I_{L_IOB}			-1		1	μA
Voltage Comparator Threshold	V_CMP	IOA operation only. After POR or SEL = 0.		3.7	4	4.3	V
High-Voltage Detection Maximum Ramp	t_HVR	IOA; V_TH to V_CMP with V_L = 1.8V and DIV1			298		μs
		IOA; V_TH to V_CMP with V_L = 1.8V and DIV2			646
		IOA; V_TH to V_CMP with V_L = 1.8V and DIV4			1330
		IOA; V_TH to V_CMP with V_L = 1.8V and DIV8			2610
High-to-Low Switching Threshold	V_TL	IOA; V_PUP = V_PUPA, IOB; V_PUP = V_L (Note 5, Note 6)			0.65 x V_PUP		V
Input Low Voltage	V_IL	IOA; V_PUP = V_PUPA, IOB; V_PUP = V_L(Note 7)				0.1 x V_PUP	V
Low-to-High Switching Threshold	V_TH	IOA; V_PUP = V_PUPA, IOB; V_PUP = V_L (Note 5, Note 8)			0.75 x V_PUP		V
Switching Hysteresis	V_HY	(Note 5, Note 9)			0.3		V
Output Low Voltage	V_OL	I_OL = 4mA (Note 10)				0.4	V
Propagation Delay	t_OVL-VDD	Pass-through mode only				600	ns
Propagation Delay	t_OVDD-VL	Pass-through mode only				600	ns
Maximum Data Rate	t_DR	Pass-through mode only, R_PUP = 680Ω				512	kbps
IOA SENSE
IOA Weak Pullup/Pulldown	R_WRES-DN				5		MΩ
IOA Weak Pullup/Pulldown	R_WRES-UP				0.5		MΩ
Input Low	SENSE_V_IL					0.2	V
Input High	SENSE_V_IH			0.8		V_PUPA + 0.3	V
IOA, IOB PINS: 1-Wire INTERFACE
Recovery Time	t_REC	(Note 11)	R_PUPA = 1000Ω, V_L not powered	5			μs
		(Note 11)	R_PUPB = 1000Ω, V_L powered	1
		(Note 11)	Directly prior to reset pulse; R_PUPA = 1000Ω; V_L not powered	50
Rising-Edge Hold-Off	t_REH	Overdrive speed (Note 12)			100		ns
Time Slot Duration	t_SLOT	Overdrive speed (Note 13)		11			μs
IOA, IOB PINS: 1-Wire RESET, PRESENCE-DETECT CYCLE
Reset Low Time	t_RSTL	System requirement, overdrive speed	V_L powered	48		80	μs
Reset Low Time	t_RSTL	System requirement, overdrive speed	V_L not powered	48		50	μs
Reset High Time	t_RSTH	Overdrive speed (Note 17)		48			μs
Presence-Detect Sample Time	t_MSP	Overdrive speed (Note 14)		6		10	μs
Presence Detect Fall Time	t_FPD	GBD	Overdrive speed (Note 18)		0.15		μs
IO PIN: 1-Wire WRITE
Write-Zero Low Time	t_W0L	Overdrive speed (Note 15)		6		15.5	μs
Write-One Low Time	t_W1L	Overdrive speed (Note 15)		0.25		2	μs
IOA, IOB PINS: 1-Wire READ
Read Low Time	t_RL	Overdrive speed (Note 16)		0.25		2 - δ	μs
Read Sample Time	t_MSR	Overdrive speed (Note 16)		t_RL+ δ		2	μs
PIOA, PIOB PINS
GPIO Output Low	PIOV_OL	PIOI_OL = 4mA (Note 10)				0.4	V
GPIO Input Low	PIOV_IL			-0.3		0.2 x V_L	V
GPIO Controller Sample	PIOV_IH			0.80 x V_L		V_L + 0.3	V
GPIO Switching Hysteresis	PIOV_HY				0.1 x V_L		V
GPIO Leakage Current	PIOI_L	(Note 21)		-1		+1	μA
PIO Delay	t_P	GBD			0.2		μs
CD/PIOC PIN
Output Low	CD_PIOV_OL	CD_PIOI_OL = 4mA (Note 10)				0.4	V
Input Low	CD_PIOV_IL			-0.3		0.20 x V_PUPA	V
Input High	CD_PIOV_IH			0.8 x V_PUPA		V_PUPA + 0.3	V
CD_PIO Switching Hysteresis	CD_PIOV_HY				0.1 x V_PUPA		V
Leakage Current	CD_PIOI_L			-1		+1	μA
CD_PIO Delay	t_P	GBD			0.2		μs
TOKEN PIN
Output Low	TOKENV_OL	TOKENI_OL = 4mA (Note 10)				0.4	V
Leakage Current	TOKENI_L			-1		+1	μA
Token Frequency	TOK_F	Pass-through mode only			30k		Hz
TIMER
Timer Period	t_TP			89.1	99	108.9	μs
IOA PIN: STRONG PULLUP APPLIED DURING POWER-UP
Strong Pullup Current	I_SPU	(Note 19)				500	μA
Strong Pullup Voltage	V_SPU	(Note 19)		1.71			V
Warmup Time	t_OSCWUP	(Note 1, Note 20)				5	ms

Note 1:	Initial power-up from IOA requires strong pullup for t_OSCWUP duration.
Note 2:	System requirement. Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times.
Note 3:	Value represents the typical supply capacitance when IOA or V_L is first applied. Once the supply capacitance is charged, it does not affect normal communication. Typically, during normal communication, the parasite capacitance is effectively ~100pF.
Note 4:	Internal supply (V_REG) will move to IOA parasite power (V_DD) if IOA is greater than V_L.
Note 5:	IOA V_TL, V_TH, and V_HY are a function of the internal parasite supply voltage (V_DD), which is a function of V_PUPA, R_PUPA, 1-Wire timing, and capacitive loading on IOA. Lower V_PUPA, higher R_PUPA, shorter t_REC, and heavier capacitive loading all lead to lower values of V_TL, V_TH, and V_HYfor the IOA link. V_TL, V_TH, and V_HY are a function of the V_L for the IOB link.
Note 6:	Voltage below which, during a falling edge on IO, a logic-zero is detected.
Note 7:	The average voltage on IO must be less than or equal to V_ILMAX at all times the controller is driving IO to a logic-zero level.
Note 8:	Voltage above which, during a rising edge on IO, a logic-one is detected.
Note 9:	After V_TH is crossed during a rising edge on IO, the voltage on IO must drop by at least V_HY to be detected as logic-zero.
Note 10:	The I-V characteristic is linear for voltages less than 1V.
Note 11:	System requirement. Applies to a single device attached to a 1-Wire line.
Note 12:	The earliest recognition of a negative edge is possible at t_REH after V_TH has been previously reached.
Note 13:	Defines maximum possible bit rate. Equal to 1/(t_W0LMIN + t_RECMIN).
Note 14:	System requirement. Interval after t_RSTL during which a bus controller can read a logic 0 on IO if there is a DS2488 present. Communication should not begin to after the 2ms power-up for IOA has completed when no V_L is present.
Note 15:	System requirement. ε in Figure 7 represents the time required for the pullup circuitry to pull the voltage on IO up from V_IL to V_TH. The actual maximum duration for the controller to pull the line low is t_W1LMAX + t_F - ε and t_W0LMAX + t_F - ε, respectively.
Note 16:	System requirement. δ in Figure 7 represents the time required for the pullup circuitry to pull the voltage on IO up from V_IL to the input-high threshold of the bus controller. The actual maximum duration for the controller to pull the line low is t_RLMAX + t_F.
Note 17:	An additional reset or communication sequence cannot begin until the reset high time has expired.
Note 18:	Time from V_(IO) = 80% of V_PUP and V_(IO) = 20% of V_PUP at the negative edge on IOA or IOB at the beginning of the presence detect pulse.
Note 19:	I_SPU is the current drawn from IOA during a strong pullup (SPU) operation before 3ms has elapsed during a power-up when V_L has no supply. The pullup circuit on IO during the SPU operation should be such that the voltage at IOA is greater than or equal to V_SPUMIN. A low-impedance bypass of R_PUPA activated during the SPU operation is the recommended way to meet this requirement.
Note 20:	1-Wire communication should not take place for the max t_OSCWUP time following a power-on reset. If powering up on IOA only, SPU is required for this duration. If powering up on IOA only, charge sensing typically occurs at 1.5ms.
Note 21:	PIOB must be less or equal to V_L. If PIOB > V_L, I_VL will be incurred on PIOB.

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{"data-trigger":"hover","data-placement":"right","data-toggle":"popover","data-original-title":"\u003cstrong\u003eNote 2\u003c/strong\u003e","data-html":true,"data-content":"System requirement. Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times."}

{"data-trigger":"hover","data-placement":"right","data-toggle":"popover","data-original-title":"\u003cstrong\u003eNote 3\u003c/strong\u003e","data-html":true,"data-content":"Value represents the typical supply capacitance when IOA or VL is first applied. Once the supply capacitance is charged, it does not affect normal communication. Typically, during normal communication, the parasite capacitance is effectively ~100pF."}

{"data-trigger":"hover","data-placement":"right","data-toggle":"popover","data-original-title":"\u003cstrong\u003eNote 4\u003c/strong\u003e","data-html":true,"data-content":"Internal supply (VREG) will move to IOA parasite power (VDD) if IOA is greater than VL."}

{"data-trigger":"hover","data-placement":"right","data-toggle":"popover","data-original-title":"\u003cstrong\u003eNote 5\u003c/strong\u003e","data-html":true,"data-content":"IOA VTL, VTH, and VHY are a function of the internal parasite supply voltage (VDD), which is a function of VPUPA, RPUPA, 1-Wire timing, and capacitive loading on IOA. Lower VPUPA, higher RPUPA, shorter tREC, and heavier capacitive loading all lead to lower values of VTL, VTH, and VHY for the IOA link. VTL, VTH, and VHY are a function of the VL for the IOB link."}

{"data-trigger":"hover","data-placement":"right","data-toggle":"popover","data-original-title":"\u003cstrong\u003eNote 6\u003c/strong\u003e","data-html":true,"data-content":"Voltage below which, during a falling edge on IO, a logic-zero is detected."}

{"data-trigger":"hover","data-placement":"right","data-toggle":"popover","data-original-title":"\u003cstrong\u003eNote 7\u003c/strong\u003e","data-html":true,"data-content":"The average voltage on IO must be less than or equal to VILMAX at all times the controller is driving IO to a logic-zero level."}

{"data-trigger":"hover","data-placement":"right","data-toggle":"popover","data-original-title":"\u003cstrong\u003eNote 8\u003c/strong\u003e","data-html":true,"data-content":"Voltage above which, during a rising edge on IO, a logic-one is detected."}

{"data-trigger":"hover","data-placement":"right","data-toggle":"popover","data-original-title":"\u003cstrong\u003eNote 9\u003c/strong\u003e","data-html":true,"data-content":"After VTH is crossed during a rising edge on IO, the voltage on IO must drop by at least VHY to be detected as logic-zero."}

{"data-trigger":"hover","data-placement":"right","data-toggle":"popover","data-original-title":"\u003cstrong\u003eNote 10\u003c/strong\u003e","data-html":true,"data-content":"The I-V characteristic is linear for voltages less than 1V."}

{"data-trigger":"hover","data-placement":"right","data-toggle":"popover","data-original-title":"\u003cstrong\u003eNote 11\u003c/strong\u003e","data-html":true,"data-content":"System requirement. Applies to a single device attached to a 1-Wire line."}

{"data-trigger":"hover","data-placement":"right","data-toggle":"popover","data-original-title":"\u003cstrong\u003eNote 12\u003c/strong\u003e","data-html":true,"data-content":"The earliest recognition of a negative edge is possible at tREH after VTH has been previously reached."}

{"data-trigger":"hover","data-placement":"right","data-toggle":"popover","data-original-title":"\u003cstrong\u003eNote 13\u003c/strong\u003e","data-html":true,"data-content":"Defines maximum possible bit rate. Equal to 1/(tW0LMIN + tRECMIN)."}

{"data-trigger":"hover","data-placement":"right","data-toggle":"popover","data-original-title":"\u003cstrong\u003eNote 17\u003c/strong\u003e","data-html":true,"data-content":"An additional reset or communication sequence cannot begin until the reset high time has expired."}

{"data-trigger":"hover","data-placement":"right","data-toggle":"popover","data-original-title":"\u003cstrong\u003eNote 14\u003c/strong\u003e","data-html":true,"data-content":"System requirement. Interval after tRSTL during which a bus controller can read a logic 0 on IO if there is a DS2488 present. Communication should not begin to after the 2ms power-up for IOA has completed when no VL is present."}

{"data-trigger":"hover","data-placement":"right","data-toggle":"popover","data-original-title":"\u003cstrong\u003eNote 18\u003c/strong\u003e","data-html":true,"data-content":"Time from V(IO) = 80% of VPUP and V(IO) = 20% of VPUP at the negative edge on IOA or IOB at the beginning of the presence detect pulse."}

{"data-trigger":"hover","data-placement":"right","data-toggle":"popover","data-original-title":"\u003cstrong\u003eNote 15\u003c/strong\u003e","data-html":true,"data-content":"System requirement. ε in Figure 7 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to VTH. The actual maximum duration for the controller to pull the line low is tW1LMAX + tF - ε and tW0LMAX + tF - ε, respectively."}

{"data-trigger":"hover","data-placement":"right","data-toggle":"popover","data-original-title":"\u003cstrong\u003eNote 16\u003c/strong\u003e","data-html":true,"data-content":"System requirement. δ in Figure 7 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to the input-high threshold of the bus controller. The actual maximum duration for the controller to pull the line low is tRLMAX + tF."}

{"data-trigger":"hover","data-placement":"right","data-toggle":"popover","data-original-title":"\u003cstrong\u003eNote 21\u003c/strong\u003e","data-html":true,"data-content":"PIOB must be less or equal to VL. If PIOB \u003e VL, IVL will be incurred on PIOB."}

{"data-trigger":"hover","data-placement":"right","data-toggle":"popover","data-original-title":"\u003cstrong\u003eNote 19\u003c/strong\u003e","data-html":true,"data-content":"ISPU is the current drawn from IOA during a strong pullup (SPU) operation before 3ms has elapsed during a power-up when VL has no supply. The pullup circuit on IO during the SPU operation should be such that the voltage at IOA is greater than or equal to VSPUMIN. A low-impedance bypass of RPUPA activated during the SPU operation is the recommended way to meet this requirement."}

{"data-trigger":"hover","data-placement":"right","data-toggle":"popover","data-original-title":"\u003cstrong\u003eNote 20\u003c/strong\u003e","data-html":true,"data-content":"1-Wire communication should not take place for the max tOSCWUP time following a power-on reset. If powering up on IOA only, SPU is required for this duration. If powering up on IOA only, charge sensing typically occurs at 1.5ms."}

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stroke-linejoin: round; stroke-width: 0.5;'/\u003e\n\t\t\t\u003c/g\u003e\n\t\t\t\u003cg id='svg11-shape143-558' transform='translate(-425.659,264.923) rotate(-63.4349)' v:groupContext='shape' v:mID='143'\u003e\n\t\t\t\t\u003ctitle\u003eSheet.143\u003c/title\u003e\n\t\t\t\t\u003cpath d='M-0 478.42 A4.5 2.25 -26.57 0 0 5.03 478.42 L0 478.42 Z' style='fill: none;'/\u003e\n\t\t\t\t\u003cpath d='M-0 478.42 A4.5 2.25 -26.57 0 0 5.03 478.42' style='stroke: #000000; stroke-linecap: round; stroke-linejoin: round; stroke-width: 0.5;'/\u003e\n\t\t\t\u003c/g\u003e\n\t\t\u003c/g\u003e\n\t\u003c/g\u003e\n\u003c/svg\u003e\u003c/div\u003e\n\u003cfigcaption\u003eFigure 7. Read/Write Timing Diagrams\u003c/figcaption\u003e\n\u003c/figure\u003e\u003c/div\u003e","data-container":"body"}