Detailed Description

The DS2488 fundamentally operates from two independent 1-Wire peripheral interfaces, IOA and IOB, which operate with a token defined arbitration scheme as detailed in the state machine diagram of Figure 1 and truth table of Table 1. Depending on which side of the link has the token assigned, IOA or IOB, that side has control for 1-Wire communication with the device; see Pin Description for token state assignment definition. With control, writes and reads to the DS2488 communication buffer and registers are performed to exchange small messages between IOA and IOB, set configuration parameters, read/write to the three GPIO pins, and set the timeout value of a timer used in conjunction with a high-speed 512kbps pass-through mode between IOA and IOB. Once set into pass-through mode, the timer is reset with each falling edge at IOA or IOB to maintain the mode. This enables simplex (one direction only) or half duplex (devices take turns transmitting and receiving) UART-to-UART communication to pass large amounts of data. See the Simplified Application Block Diagram and TWS Application Circuit example for the hardware configuration of the UART interface of each subsystem controller to operate under software control, either as a 1-Wire controller or UART transceiver.

Like typical 1-Wire products, the DS2488 has operational modes whereby device power is parasitically captured from the 1-Wire interface. However, this applies only to communication and operation through the IOA interface, not IOB. When communicating 1-Wire commands to the IOB interface, or when operating in the high-speed pass-through mode, an additional supply in (V_L) is required (see the Power-Supply Description section. Also, as a 1-Wire product, the DS2488 provides a unique 64-bit registration number (ROM ID) that is factory-programmed into the device. The ROM ID serves an important role in applications such as TWS where two DS2488 devices, one in each earbud, would be multidrop connected to the same 1-Wire connection originating from the charging case controller. For this scenario, the ROM ID is used by the case controller to select the specific DS2488 in the left or right earbud for communication and operation. Additionally, the unique serialization field that is a data component of the 64-bit ROM ID can be used for end-product identification and traceability.

For applications that require power to be sourced from the IOA subsystem side to the IOB side, the device provides a configurable mode that enables a 4V to 5V supply to be switched through an external transistor that is controlled from a DS2488 signal (CD/PIOC). For normal 1-Wire and pass-through mode communication, the DS2488 operating voltage range is 1.71V to 3.63V. However, to support this power delivery mode, the device is 5V tolerant and goes into the power delivery state when 4V to 5V (nom) is detected at IOA. An integrated comparator is used for this detection and control of the CD/PIOC pin.

A state machine controls the internal operations per Figure 1. The device starts in the POR state on power-up through V_L or IOA parasite power. Communication is ignored during the POR t_OSCWUP time as the device initializes. The warmup delay only occurs on power-up. State transitions are made on the internal 30kHz oscillator. State transitions take multiple clocks, especially high-voltage detection, and enable pass-through mode. The timer function runs on a 10kHz divide of the oscillator. After the POR warm-up, if SEL = 0 (default), the device checks for high voltage on the IOA link. If high voltage is detected, the charge function is activated, and IOB link is handed the token for communication. The IOB link generates a presence detect when IOA passes the token to IOB. If high voltage is not detected, IOB does not have the token and the state machine checks the config bits QM/PTM/PULLUP and branches accordingly. If the config mode bits are not set and IOA is high, IOA is handed the token for communication. The IOA channel does not issue a presence detect when it has the token to avoid contention with the charging function. IOA communication stays active until IOA times out low, either from the IOA controller pulling low or the weak pulldown on a floating IOA. The IOA weak pulldown is normally active, except during charge sensing, pass-through mode, and the IOA PULLUP mode. If IOA is not connected or times out low, IOB is given the token for communication until IOA goes high. When IOA goes high, the device loops back to the SEL = 0, the IOA high-voltage charge-sense function.

The timer is used to monitor the IOA pin for transitioning into IOB '1-Wire Operation' state. A falling edge on IOA resets the timer. If the timer expires and confirms that a logic low is still present, then the IOB link is passed the token (i.e., no other falling-edge transition occurred). While IOB link has the token, the IOA controller continues to pull low. However, if the IOA controller drives high before the timer expires, then the logic state will exit to the appropriate state (e.g., IOA link state "Idle logic high") when the timer expires. See Table 1 for more details on the states.

Each DS2488 contains a unique ROM ID that is 64 bits long. The ROM ID provides absolute traceability for each device. The first 8 bits are a 1-Wire family code. The next 48 bits are a unique serial number. The last 8 bits are a cyclic redundancy check (CRC) of the first 56 bits. See Figure 2 for details. The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and XOR gates. The polynomial is X⁸ + X⁵ + X⁴ + 1. Additional information about the 8-bit, 1-Wire CRC is available in Application Note 27.

After a 1-Wire Reset/Presence cycle and ROM function command sequence are successful, a device function command can be accepted. The commands generally follow the Figure 3 flow.

There are nine device function commands that are summarized in Table 2 and are described in detail in subsequent sections. Within the Figure 3 flow diagram, the data transfer is verified when writing and reading by a CRC of 16-bit type (CRC-16). The CRC-16 is computed as described in Application Note 27.

The Write Configuration command is used to set the configuration register.

Bit 0: Select (SEL). When set to 1, PIOC pin function is operational. When set to 0 (default), CD pin function is operational.

Bit 1: BUFA Port Enable (BUFAPE). When set to 1, the PIOA pin outputs the invert state of the BUFA flag in the status register. When set to 0 (Default), the PIOA pin is normal access.

Bit 2: BUFB Port Enable (BUFBPE). When set to 1, the PIOB pin outputs the invert state of the BUFB flag in the status register. When set to 0 (Default), the PIOB pin will be normal access.

Bit 3: Pass-Through Mode (PTM). When set to 1, PTM is enabled and the timer begins to monitor IOA/IOB pins for activity (i.e., falling-edge transitions) and outputs a clock on the TOKEN pin. The timer resets on any falling-edge activity to maintain PTM. If no activity occurs, then the device automatically returns to normal 1-Wire operation states and the PTM bit is cleared to 0 when the timer expires. When set to 0 (Default), pass-through mode is disabled.

Bit 4: Quiet Mode (QM). When set to 1, QM is enabled and the timer begins to monitor the IOA pin for activity (i.e., falling-edge transitions) and outputs logic high on the TOKEN pin. The timer is reset on any IOA pin falling-edge activity to the timeout value so as to maintain QM. If no other falling-edge IOA activity occurs, then the device automatically returns to normal 1-Wire operation states, and the QM bit is cleared to 0 when the timer expires. This bit defaults to 0.

Bit 5: Pullup (PULLUP). When set to 1, a weak pullup resistor from the IOA link to V_REG is enabled. When set to 0 (Default), the pullup resistor is disconnected from V_REG and the weak pulldown to ground is connected. In this way, the IOA pin is not floating when not connected to any equipment. The write config CRC-16 may read invalid or FF when setting PULLUP = 1, and should be ignored. This is due to the resulting TWS state transition.

The Read Configuration command is used to read the configuration register.

Bit 0: Select (SEL). Read bit state.

Bit 1: BUFA Port Enable (BUFAPE). Read bit state.

Bit 2: BUFB Port Enable (BUFBPE). Read bit state.

Bit 3: Pass-Through Mode (PTM). Read bit state.

Bit 4: Quiet Mode (QM). Read bit state.

Bit 5: Pullup (PULLUP). Read if pullup resistor is connected (1) or disconnected (0).

The Write Buffer command is used to write a temporary value to the volatile buffer. The buffer is used to transfer bytes to/from the 1-Wire IOA or IOB link.

Bits 3:0: Byte Length (BLEN). Data length to write, 0 to maximum length number of 8.

The Read Buffer command is used to read  the buffer from the 1-Wire IOB link or from the 1-Wire IOA link.

Bits 3:0: Byte Length (BLEN). These bits represent the number of bytes to be read.

The Read Status command indicates which interface wrote the buffer last, and also the logical state of the IOA/IOB input buffers, high-voltage comparator state, token state, timer reset, and power source.

Bit 0: Buffer A Flag (BUFA).  Indicates the buffer was written from the IOA link.

Bit 1: Buffer B Flag (BUFB).  Indicates the buffer was written from the IOB link.

Bit 2: IOA State (IOAS).  Logic state of the IOA pin.

Bit 3: IOB State (IOBS).  Logic state of an AND gate with the IOB and V_L pins as the inputs.

Bit 4: Comparator State (CMPS).  Output state of the comparator. This can be used to detect charging voltage when 1 and no charging voltage when 0 on the IOA pin.

Bit 5: Token State (TOKS).  Logic state of the TOKEN pin. Toggles when in PTM.

Bit 6: Timer Reset (TRST).  In logic-low state, this indicates the timer has begun again with the timeout value. This flag is synchronously set after a status read so a read status must be performed to first set the bit, followed by a second read status to see if the bit remains set (the timer is running), or clears (the timer is not running yet, or started since previous read status).

Bit 7: Power Source (PSW).  Indicates when set that the V_L pin is being used as the power source. When 0, the power source is parasitically derived by the IOA link.

The PIO Write command controls the open-drain PIO drive state if a special function is not active on the pin. See write config bits SEL, BUFBPE, and BUFAPE for a description of the special functions. To switch the output transistor on, the corresponding bit value is 0. To switch the output transistor off (nonconducting), the bit must be 1. This way, the bit transmitted as the new PIO output state arrives in its true form at the PIO pin. The actual PIO transition to the new state occurs with a delay of t_REH+t_P from the rising edge of the MS bit of the inverted PIO byte, as shown in Figure 4.

Bit 0: PIOA Output State (PIOAS).  Set this bit to 0 for conducting (logic low) or set this bit to 1 (default) for nonconducting (high impedance or logic high with external pullup).

Bit 1: PIOB Output State (PIOBS).  Set this bit to 0 for conducting (logic low) or set this bit to 1 (default) for nonconducting (high impedance or logic high with external pullup).

Bit 2: PIOC Output State (PIOCS).  Set this bit to 0 for conducting (logic low) or set this bit to 1 (default) for nonconducting (high impedance or logic high with external pullup).

The PIO Read command reads the input logic state of the PIO pins. V_L must be active to read the PIOA and PIOB input logic state. The IOA parasite supply must be active to read the PIOCS input logic state. PIO input buffers read high if the associated supply is not active. The PIO input buffers are normally off to prevent crowbar current, and are turned on briefly to read the input logic state.

Bit 0: PIOA Level (PIOAL).  Provides the logic state of the PIOA pin.

Bit 1: PIOB Level (PIOBL).  Provides the logic state of the PIOB pin.

Bit 2: PIOC Level (PIOCL).  Provides the logic state of the PIOC or CD pin.

The Write Timeout Value command is used to set the timer duration.

Bits 7:0: Timeout Value (TVAL).  Sets the end value for the timer. Defaults to FFh. Timer timeout value has the following meaning:

Timer Duration = TVAL x 100μs

The Read Timeout Value command is used to read the timer duration.

Bits 7:0: Timeout Value (SVAL).  Read the timeout value as specified:

Timer Duration = TVAL x 100μs

The 1-Wire bus is a system that has a single bus controller and one or more peripherals. In all instances, the DS2488 is a peripheral device. The bus controller is typically a microcontroller. The discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire signaling (signal types and timing). The 1-Wire protocol defines bus transactions in terms of the bus state during specific time slots that are initiated on the falling edge of sync pulses from the bus controller.

The 1-Wire bus has only a single line by definition; it is important that each device on the bus can drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open-drain or three-state outputs. Both 1-Wire ports (IOA and IOB) are open drain with an internal circuit equivalent as shown in Figure 5.

A multidrop bus consists of a 1-Wire bus with multiple peripherals attached. The DS2488 supports overdrive communication speed of 90.9kbps (max). The value of the pullup resistor primarily depends on the network size and load conditions. The DS2488 requires a pullup resistor.

The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus must be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low for more than 15.5μs (overdrive speed), one or more devices on the bus could be reset.

The protocol for accessing the DS2488 through either IOA or IOB 1-Wire ports is as follows:

• Initialization
• ROM Function command
• Device Function command
• Transaction/data

All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a reset pulse transmitted by the bus controller followed by presence pulse(s) transmitted by the peripheral(s). The presence pulse lets the bus controller know that the DS2488 is on the bus and is ready to operate. For more details, see the following 1-Wire Signaling and Timing section.

The DS2488 requires strict protocols to ensure data integrity. The protocol consists of four types of signaling on one line: reset sequence with reset pulse and presence pulse, write-zero, write-one, and read-data. Except for the presence pulse, the bus controller initiates all falling edges. The DS2488 can communicate at overdrive speed when not in pass-through mode.

To get from idle to active, the voltage on the 1-Wire line needs to fall from V_PUP below the threshold V_TL. To get from active to idle, the voltage needs to rise from V_ILMAX past the threshold V_TH. The time it takes for the voltage to make this rise is seen in Figure 7 as ε, and its duration depends on the pullup resistor (R_PUP) used and the capacitance of the 1-Wire network attached. The voltage V_ILMAX is relevant for the DS2488 when determining a logic level, not triggering any events.

Figure 6 shows the initialization sequence required to begin any communication with the DS2488. A reset pulse followed by a presence pulse indicates that the DS2488 is ready to receive data, given the correct ROM and device function command. If the bus controller uses slew-rate control on the falling edge, it must pull down the line for t_RSTL + t_F to compensate for the edge. The DS2488's t_RSTL is no longer than 80μs.

After the bus controller has released the line, it goes into receive mode. Now, the 1-Wire bus is pulled to V_PUP through the pullup resistor or, in the case of a special driver chip, through the active circuitry. Now, the 1-Wire bus is pulled to V_PUP through the pullup resistor. When the threshold V_TH is crossed, the DS2488 waits and then transmits a presence pulse by pulling the line low. To detect a presence pulse, the controller must test the logical state of the 1-Wire line at t_MSP.

Immediately after t_RSTH has expired, the DS2488 is ready for data communication. In a mixed population network, t_RSTH should be extended to a minimum 48μs at overdrive speed to accommodate other 1-Wire devices.

Data communication with the DS2488 takes place in time slots that carry a single bit each. Write time slots transport data from bus controller to peripheral. Read time slots transfer data from peripheral to controller. Figure 7 illustrates the definitions of the write and read time slots.

All communication begins with the controller pulling the data line low. As the voltage on the 1-Wire line falls below the threshold V_TL, the DS2488 starts its internal timing generator that determines when the data line is sampled during a write time slot and how long data is valid during a read time slot.

A read-data time slot begins like a write-one time slot. The voltage on the data line must remain below V_TL until the read low time t_RL is expired. During the t_RL window, when responding with a 0, the DS2488 starts pulling the data line low; its internal timing generator determines when this pulldown ends and the voltage starts rising again. When responding with a 1, the DS2488 does not hold the data line low at all, and the voltage starts rising as soon as t_RL is over.

The sum of t_RL + δ (rise time) on one side and the internal timing generator of the DS2488 on the other side define the controller sampling window (t_MSRMIN to t_MSRMAX), in which the controller must perform a read from the data line. For the most reliable communication, t_RL should be as short as permissible, and the controller should read close to, but no later than t_MSRMAX. After reading from the data line, the controller must wait until t_SLOT is expired. This guarantees sufficient recovery time t_REC for the DS2488 to get ready for the next time slot. Note that t_REC specified herein applies only to a single DS2488 attached to a 1-Wire line. For multidevice configurations, t_REC must be extended to accommodate the additional 1-Wire device input capacitance. Alternatively, an interface that performs active pullup during the 1-Wire recovery time, such as the special 1-Wire line drivers, can be used.

Once the bus controller has detected a presence, it can issue one of the five ROM function commands that the DS2488 supports. All ROM function commands are 8 bits long. For operational details, see Figure 8. A descriptive list of these ROM function commands follows in the subsequent sections and the commands are summarized in Table 30.

When a system is initially brought up, the bus controller might not know the number of devices on the 1-Wire bus or their ROM ID numbers. By taking advantage of the wired-AND property of the bus, the controller can use a process of elimination to identify the ID of all peripheral devices. For each bit in the ID number, starting with the least significant bit, the bus controller issues a triplet of time slots. On the first slot, each peripheral device participating in the search outputs the true value of its ID number bit. On the second slot, each peripheral device participating in the search outputs the complemented value of its ID number bit. On the third slot, the controller writes the true value of the bit to be selected. All peripheral devices that do not match the bit written by the controller stop participating in the search. If both of the read bits are zero, the controller knows that peripheral devices exist with both states of the bit. By choosing which state to write, the bus controller branches in the search tree. After one complete pass, the bus controller knows the ROM ID number of a single device. Additional passes identify the ID numbers of the remaining devices. Refer to Application Note 187: 1-Wire Search Algorithm for a detailed discussion, including an example.

The Read ROM command allows the bus controller to read the DS28E38’s 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This command can only be used if there is a single peripheral on the bus. If more than one peripheral is present on the bus, a data collision occurs when all peripherals try to transmit at the same time (open drain produces a wired-AND result). The resultant family code and 48-bit serial number result in a mismatch of the CRC.

The Match ROM command, followed by a 64-bit ROM sequence, allows the bus controller to address a specific DS2488 on a multidrop bus. Only the DS2488 that exactly matches the 64-bit ROM sequence responds to the subsequent device function command. All other peripherals wait for a reset pulse. This command can be used with a single device or multiple devices on the bus.

This command can save time in a single-drop bus system by allowing the bus controller to access the device functions without providing the 64-bit ROM ID. If more than one peripheral is present on the bus and, for example, a read command is issued following the Skip ROM command, data collision occurs on the bus as multiple peripherals transmit simultaneously (open-drain pulldowns produce a wired-AND result).

To maximize the data throughput in a multidrop environment, the Resume command is available. This command checks the status of the RC bit and, if it is set, directly transfers control to the device function commands, similar to a Skip ROM command. The only way to set the RC bit is through successfully executing the Match ROM, Search ROM, or Overdrive-Match ROM command. Once the RC bit is set, the device can repeatedly be accessed through the Resume command. Accessing another device on the bus clears the RC bit, preventing two or more devices from simultaneously responding to the Resume command.

In a 1-Wire environment, line termination is possible only during transients controlled by the bus controller (1-Wire driver). 1-Wire networks, therefore, are susceptible to noise of various origins. Depending on the physical size and topology of the network, reflections from end points and branch points can add up or cancel each other to some extent. Such reflections are visible as glitches or ringing on the 1-Wire communication line. Noise coupled onto the 1-Wire line from external sources can also result in signal glitching. A glitch during the rising edge of a time slot can cause a peripheral device to lose synchronization with the controller and, consequently, result in a Search ROM command coming to a dead end or cause a device-specific function command to abort. For better performance in network applications, the DS2488 uses a 1-Wire front-end that is less sensitive to noise. The IOA/IOB 1-Wire front-end has hysteresis, and a rising-edge hold-off delay.

• On the low-to-high transition, if the line rises above V_TH but does not go below V_TL, the glitch is filtered (Figure 9, Case A.)

• The rising-edge hold-off delay (nominally 100ns), t_REH, filters glitches that go below V_TL before t_REH has expired (Figure 9, Case B). Effectively, the device does not see the initial rise, and the t_REH delay resets when the line goes below V_TL.

• If the line goes below V_TL after t_REH has expired, the glitch is not filtered and is taken as the beginning of a new time slot (Figure 9, Case C.)

Independent of the time slot, the falling edge of the presence pulse has a controlled slew rate to reduce ringing. The falling delay is specified by t_FPD.

In some cases, it may be convenient to slow down the internal clock cycle time. One good example would be if an application has a load switch with a slow rise time to power the battery charger. The default high-voltage detection maximum ramp (t_HVR) may be too fast and sample the IOA pin early before properly reaching the V_CMP threshold, thus causing the device to remain out of the "charge state" with the CD pin nonconducting.

To overcome this, the DS2488 factory setting of the internal oscillator is alterable. This directly affects the timing of the charging state, timer duration, token frequency, and PTM, but not the 1-Wire timing. The default after POR is the 30kHz internal oscillator (DIV1). This oscillator can be divided into volatile memory by 2, 4, or 8. The setting can be adjusted by sending a 1-Wire sequence to IOA or the IOB link. This must be done after each POR of the device.

Table 31 shows the 1-Wire sequence options to set the oscillator division configuration:

RP = 1-Wire reset cycle with presence pulse

XX = Transmit byte (hex)

X = Single transmit bit (bin)

[XX] = Receive byte (for example the CRC returned by the DS2488)

<DELAY Xms> = Delay required by the 1-Wire sequence