| Package Code | TD1232MY+1 |
| Outline Number | 21-100369 |
| Land Pattern Number | 90-100136 |
| Thermal Resistance, Four-Layer Board: | |
| Junction-to-Ambient (θJA) | 62.75°C/W |
| Junction-to-Case Thermal Resistance (θJC) | 8.27°C/W |
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
data-opMAX40027ATC%2FVY%2BT
data-opMAX40027ATC%2FVY%2B
Ground. Signal and power return. Connect pins 1 and 4 together externally.Comparator 1 Non-Inverting InputComparator 1 Inverting InputComparator 2 Non-Inverting InputComparator 2 Inverting InputPositive Supply. Connect pins 7 and 10 together externally.Comparator 2 Inverting LVDS Output. Connect a 100Ω termination resistor between OUT2- and OUT2+. OUT2- is at logic-low if VIN2+ is at higher voltage compared to VIN2-.Comparator 2 Non-Inverting LVDS Output. Connect a 100Ω termination resistor between OUT2+ and OUT2-. OUT2+ is at logic-high if VIN2+ is at higher voltage compared to VIN2-.Comparator 1 Inverting LVDS Output. Connect a 100Ω termination resistor between OUT1- and OUT1+. OUT1- is at logic-low if VIN1+ is at higher voltage compared to VIN1-.Comparator 1 Non-Inverting LVDS Output. Connect a 100Ω termination resistor between OUT1+ and OUT1-. OUT1+ is at logic-high if VIN1+ is at higher voltage compared to VIN1-.Exposed Pad. This pad must be connected to ground.