Applications Information

Applications Information Critical Layout Guidelines
Some critical layout guidelines are listed below.
  • Use a PC board with a low-impedance ground plane.
  • Mount one or more 10nF ceramic capacitors between GND and VCC, as close to the pins as possible. Multiple bypass capacitors help to reduce the effect of trace impedance and capacitor ESR.
  • Choose bypass capacitors for minimum inductance and ESR.
  • Use a 100Ω termination resistor for the LVDS output, connected directly between OUTx+ and OUTx-, if practical. If the destination LVDS inputs can't be located adjacent to the outputs, use a 100Ω microstrip between the output pins and the termination resistor, which should be close to the LVDS inputs of the FPGA or other destination component. This will avoid the creation of stub beyond the termination resistor, which will cause reflections. The added length of the differential trace has less degrading affects than added stub length.
  • Ensure that there is no parasitic coupling between the inputs and the outputs. Such coupling serves as feedback, and can result in oscillation.
  • Minimize any parasitic layout inductance.
  • It is recommended to use higher performance substrate materials (for example, Rogers).
  • A differential micro-strip is the recommended layout for the MAX40027 with terminations done close to the device inputs and outputs. Care must be taken to avoid unwanted stubs by removing ground below the traces that are not part of the 50Ω termination line leading into input pins. The parasitic capacitance created between traces and ground slow down and even distort the signals by creating reflections on the path.
  • Prevent cross coupling by routing one channel inputs and outputs on the top layer, and the other channel inputs and outputs on the bottom layer.
  • Below is an example from the MAX40027EVKIT#, where ground has been etched/removed underneath a stub as shown in the layer below top layer.
Figure 7. Layout Guidelines—Ground Keep-Out to Avoid Stubs.
Input Slew Rate
With slower slew rates, when the input voltage is near the threshold any parasitic feedback paths can cause oscillation. In addition, the comparator’s input noise will cause the output to undergo transitions. Eliminating feedback paths will stop oscillation. To avoid noise-induced chattering, the input slew rate should be greater than 1V/μs.
Typical Application Circuits
Receiver Section of Differential Time-of-Flight Measurement Circuit:
In Figure 8, the photodiode, shown at the far right, converts light incident upon it into current that drives the input of the MAX40660 Transimpedance Amplifier (TIA). The MAX40660 then converts photodiode current to voltage, amplifies it, and passes a replica of the incident light to input of the  high-speed comparator. By default, the MAX40660 has -200mV differential output offset voltage when there is no input current. This offset can be adjusted using the MAX40660's offset pin. The MAX40027 produces differential output pulses whenever an incident light pulse has intensity sufficient to change the polarity of the comparator input signal.
Receiver Section of Single-Ended Time-of-Flight Measurement Circuit:

Figure 9 has a single-ended output configuration on the transimpedance amplifier, which drives one input of the comparator. This functionality is the same as that of the differential configuration discussed above, except that the threshold voltage can be adjusted by selecting the values of R1 and R2.

Figure 8. Differential-Ended Output Receiver
Figure 9. Single-Ended Output Receiver