Electrical Characteristics

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Electrical Characteristics

(Limits are 100% tested at TA = +25°C and TA = +105°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested. Specifications to the minimum operating temperature are guaranteed by design and are not production tested. General-purpose I/O are only tested at TA = +105°C.)

POWER (Refer to the MAX32650 User Guide for sequencing requirements)
Supply Voltage, Core VCORE fSYS_CLK = 120MHz 0.99 1.1 1.21 V
Supply Voltage, Analog VDDA 1.71 1.8 1.89 V
Supply Voltage, RTC VRTC 1.71 1.8 1.89 V
Supply Voltage, GPIO VDDIO 1.71 1.8 1.89 V
Supply Voltage, GPIO (High) VDDIOH 1.71 1.8 3.6 V
Power-Fail Reset Voltage VRST Monitors VCORE 0.835 V
Monitors VDDA 1.67
Monitors VRTC 1.67
Monitors VDDIO 1.67
Power Fail Reset Voltage VRST Monitors VDDB 2.95 V
Power-Fail Reset Voltage VRST Monitors VDDIOH 1.67 V
Power-On Reset Voltage VPOR Monitors VCORE 0.594 V
Monitors VDDA 1.52
Monitors VRTC 1.17
RAM Data Retention Voltage VDRV 0.81 V
VCORE Dynamic Current, Active Mode ICORE_DACT Total current into VCORE pins, fSYS_CLK = 120MHz, VCORE = 1.1V, CPU in Active mode, executing from cache; inputs tied to VSS, VDDIO, or VDDIOH; outputs source/sink 0mA 95 μA/MHz
VCORE Fixed Current, Active Mode ICORE_FACT 120MHz oscillator enabled, total current into VCORE pins, CPU in Active mode 0MHz execution; inputs tied to VSS, VDDIO, or VDDIOH; outputs source/sink 0mA  ‌VCORE = 1.0V 1200 μA
VCORE = 1.1V 1500
7.3728MHz oscillator enabled, total current into VCORE pins, CPU in Active mode 0MHz execution; inputs tied to VSS, VDDIO, or VDDIOH; outputs source/sink 0mA VCORE = 1.0V 555
VCORE = 1.1V 790
VDDA Fixed Current, Active Mode IDDA_FACT 120MHz oscillator enabled, total current into VDDA pins, CPU in Active mode 0MHz execution; inputs tied to VSS, VDDIO, or VDDIOH; outputs source/sink 0mA, VCORE and VDDA voltage monitors enabled 348 μA
7.3728MHz oscillator enabled, total current into VDDA pins, CPU in Active mode 0MHz execution; inputs tied to VSS, VDDIO, or VDDIOH; outputs source/sink 0mA, VCORE and VDDA voltage monitors enabled 39
VCORE Dynamic Current, Sleep Mode ICORE_DSLP Total current into VCORE pins, CPU in Sleep mode, standard DMA with two channels active 114 μA/MHz
VCORE Fixed Current, Sleep Mode ICORE_FSLP fSYS_CLK = 120MHz, total current into VCORE pins, CPU in Sleep mode, standard DMA with two channels active 1020 μA
fSYS_CLK = 7.3728MHz, total current into VCORE pins, CPU in Sleep mode, standard DMA with two channels active 356
VDDA Fixed Current, Sleep Mode IDDA_FSLP fSYS_CLK = 120MHz, total current into VDDA pins, CPU in Sleep mode, standard DMA with two channels active 348 μA
fSYS_CLK = 7.3728MHz, total current into VDDA pins, CPU in Sleep mode, standard DMA with two channels active 49
VCORE Dynamic Current, Background Mode ICORE_DBKG fSYS_CLK = 7.3728MHz, total current into VCORE pins, CPU in Deep-Sleep mode, SmartDMA active 66 μA/MHz
VCORE Fixed Current, Background Mode ICORE_FBKG 7.3728MHz oscillator enabled, total current into VCORE pins, CPU in Deep-Sleep mode, SmartDMA active ‌VCORE = 1.0V 224 μA
VCORE = 1.1V 330
VCORE Fixed Current, Deep-Sleep Mode ICORE_FDSL Standby state with full data retention 70 μA
VDDA Fixed Current, Deep-Sleep Mode IDDA_FDSL Standby state with full data retention, VCORE and VDDA voltage monitors enabled 132 nA
VRTC Fixed Current, Deep-Sleep Mode IDDRTC_FDSL Standby state with full data retention, VRTC = 1.8V, RTC enabled 540 nA
VCORE Fixed Current, Backup Mode ICORE_FBKU No SRAM retention (0KB) 30 μA
VDDA Fixed Current, Backup Mode IDDA_FBKU VDDA voltage monitor enabled 132 nA
VRTC Fixed Current, Backup Mode IDDRTC_FBKU RTC enabled, retention regulator off 540 nA
RTC enabled, 32KB SRAM retained, retention regulator on 720
RTC disabled, retention regulator off 156
Sleep Mode Resume Time tSLP_ON 575 ns
Deep-Sleep Mode Resume Time tDSL_ON Wake to fLPCLK 9 μs
Wake to fHSCLK 18
Backup Mode Resume Time tBKU_ON 5 ms
USB
USB Supply Voltage VDDB 3.0 3.3 3.6 V
D+, D- Pin Capacitance CIN_USB Pin to VSS 8 pF
Driver Output Resistance RDRV Steady-state drive 45 ± 10% Ω
USB / FULL SPEED
Single-Ended Input High Voltage (DP, DM) VIH_USB 2.0 V
Single-Ended Input Low Voltage (DP, DM) VIL_USB 0.6 V
Output High Voltage (DP, DM) VOH_USB RL = 1.5kΩ from DP and DM to VSS, IOH = -4mA VDDB - 0.4 VDDB V
Output Low Voltage (DP, DM) VOL_USB RL = 1.5kΩ from DP to VDDB, IOL = 4mA VSS 0.4 V
Differential Input Sensitivity VDI |DP to DM| 0.2 V
Common-Mode Voltage Range VCM Includes VDI range 0.8 2.5 V
Transition Time (Rise/Fall) D+, D- (Note 11) tRF CL = 50pF 4 20 ns
Pullup Resistor on Upstream Ports RPU 1.05 1.5 1.95 kΩ
USB / HI-SPEED
Hi-Speed Data Signaling Common-Mode Voltage Range VHSCM -50 +500 mV
Hi-Speed Squelch Detection Threshold VHSSQ Squelch detected 100 mV
No squelch detected 200
Hi-Speed Idle Level Output Voltage VHSOI -10 +10 mV
Hi-Speed Low Level Output Voltage VHSOL -10 +10 mV
Hi-Speed High Level Output Voltage VHSOH 400 ± 40 mV
Chirp-J Output Voltage (Differential) VCHIRPJ 900 ± 200 mV
Chirp-K Output Voltage (Differential) VCHIRPK -700 ± 200 mV
CLOCKS
System Clock Frequency fSYS_CLK 0.256 120,000 kHz
System Clock Period tSYS_CLK 1/fSYS_CLK ns
High-Speed Oscillator Frequency fHSCLK Measured at +25°C, 120MHz 120 ± 1 MHz
Low-Power Oscillator Frequency fLPCLK 50 MHz
7MHz Oscillator Frequency f7MCLK 7.3728 MHz
Nanoring Oscillator Frequency fNANO 8 kHz
RTC Input Frequency  f32KIN 32kHz watch crystal, CL = 6pF, ESR < 70kΩ 32.768 kHz
RTC Operating Current IRTC_ACTSLP Sleep or Active mode 0.39 μA
RTC Power Up Time tRTC_ ON 250 ms
GENERAL-PURPOSE I/O
Input Low Voltage for All GPIO VIL_VDDIO VDDIO selected as I/O supply 0.3 × VDDIO V
Input Low Voltage for All GPIO except P1.[21:18], P1.[16:11], P3.0 VIL_VDDIOH VDDIOH selected as I/O supply 0.3 × VDDIOH V
Input Low Voltage for RSTN VIL_RSTN 0.3 x VDDIO V
Input High Voltage for All GPIO VIH_VDDIO VDDIO selected as I/O supply 0.75 × VDDIO V
Input High Voltage for All GPIO except P1.[21:18], P1.[16:11], P3.0 VIH_VDDIOH VDDIOH selected as I/O supply 0.75 × VDDIOH V
Input High Voltage for RSTN VIH_RSTN 0.75 x VDDIO V
Output Low Voltage for All GPIO VOL_VDDIO VDDIO selected as I/O supply, VDDIO = 1.71V, DS[1:0] = 00, IOL = 1mA 0.2 0.4 V
VDDIO selected as I/O supply, VDDIO = 1.71V, DS[1:0] = 01, IOL = 2mA 0.2 0.4
VDDIO selected as I/O supply, VDDIO = 1.71V, DS[1:0] = 10, IOL = 4mA 0.2 0.4
VDDIO selected as I/O supply, VDDIO = 1.71V, DS[1:0] = 11, IOL = 8mA 0.2 0.4
Output Low Voltage for All GPIO except P1.[21:18], P1.[16:11], P3.0 VOL_VDDIOH VDDIOH selected as I/O supply, VDDIOH = 1.71V, DS[1:0] = 00, IOL = 1mA 0.2 0.4 V
VDDIOH selected as I/O supply, VDDIOH = 1.71V, DS[1:0] = 01, IOL = 2mA 0.2 0.4
VDDIOH selected as I/O supply, VDDIOH = 1.71V, DS[1:0] = 10, IOL = 4mA 0.2 0.4
VDDIOH selected as I/O supply, VDDIOH = 1.71V, DS[1:0] = 11, IOL = 8mA 0.2 0.4
Combined IOL, All GPIO IOL_TOTAL 48 mA
Output High Voltage for All GPIO VOH_VDDIO VDDIO selected as I/O supply, VDDIO = 1.71V, DS[1:0] = 00, IOL = -1mA VDDIO - 0.4 V
VDDIO selected as I/O supply, VDDIO = 1.71V, DS[1:0] = 01, IOL = -2mA VDDIO - 0.4
VDDIO selected as I/O supply, VDDIO = 1.71V, DS[1:0] = 10, IOL = -4mA VDDIO - 0.4
VDDIO selected as I/O supply, VDDIO = 1.71V, DS[1:0] = 00, IOL = -8mA VDDIO - 0.4
Output High Voltage for All GPIO except P1.[21:18], P1.[16:11], P3.0 VOH_VDDIOH VDDIOH selected as I/O supply, VDDIOH = 1.71V, DS[1:0] = 00, IOL = -1mA VDDIOH - 0.4 V
VDDIOH selected as I/O supply, VDDIOH = 1.71V, DS[1:0] = 01, IOL = -2mA VDDIOH - 0.4
VDDIOH selected as I/O supply, VDDIOH = 1.71V, DS[1:0] = 10, IOL = -8mA VDDIOH - 0.4
VDDIOH selected as I/O supply, VDDIOH = 1.71V, DS[1:0] = 11, IOL = -8mA VDDIOH - 0.4
Combined IOH, All GPIO IOH_TOTAL -48 mA
Input Hysteresis (Schmitt) VIHYS 300 mV
Input Leakage Current Low IIL VDDIO = 1.89V, VDDIOH = 3.6V, VDDIOH selected as I/O supply, VIN = 0V, internal pullup disabled -1000 +1000 nA
Input Leakage Current High IIH VDDIO = 1.89V, VDDIOH = 3.6V, VDDIOH selected as I/O supply, VIN = 3.6V, internal pulldown disabled -1000 +1000 nA
IOFF VDDIO = 0V, VDDIOH = 0V, VDDIO selected as I/O supply, VIN < 1.89V -1 +1 μA
IIH3V VDDIO = VDDIOH = 1.71V, VDDIO selected as I/O supply, VIN = 3.6V -2 +2
Input Pullup Resistor TMS, TCK, TDI RPU_T 25 kΩ
Input Pullup Resistor RSTN RPU_R 25 kΩ
Input Pullup/Pulldown Resistor for All GPIO RPU1 Normal resistance 25 kΩ
RPU2 Highest resistance 1 MΩ
FLASH MEMORY
Flash Erase Time tM_ERASE Mass erase 30 ms
tP_ERASE Page erase 30
Flash Programming Time per Word tPROG 32-bit programming mode, fFLC_CLK = 1MHz 60 μs
Flash Endurance 10 kcycles
Data Retention tRET TA = +85°C 10 years
ADC (DELTA-SIGMA)
Resolution 10 bits
ADC Clock Rate fACLK 0.1 8 MHz
ADC Clock Period tACLK 1/fACLK μs
Input Voltage Range VAIN AIN[3:0], ADC_CHSEL = 0-3, ADC_REFSEL = 1 VSSA + 0.05 VBG/2 V
AIN[3:0], ADC_CHSEL = 0-3, ADC_REFSEL = 0 VSSA  + 0.05 VBG
AIN[1:0], ADC_CHSEL = 4-5, ADC_REFSEL = 0 VSSA + 0.05 5.5
Input Impedance RAIN AIN[3:0], ADC_CHSEL = 0-3, ADC active 250 kΩ
AIN[1:0], ADC_CHSEL = 4-5, ADC active 40
Analog Input Capacitance CAIN Fixed capacitance to VSSA 1 pF
Dynamically switched capacitance 250 fF
Integral Nonlinearity INL -2 +2 LSb
Differential Nonlinearity DNL -1 +2 LSb
Offset Error VOS ±1 LSb
Gain Error GE ±2 LSb
ADC Active Current IADC ADC active, reference buffer enabled, input buffer disabled 210 µA
ADC Setup Time tADC_SU Any power-up of: ADC clock or ADC bias to CpuAdcStart 10 µs
ADC Output Latency tADC 1025 tACLK
ADC Sample Rate fADC 7.8 ksps
ADC Input Leakage IADC_LEAK AIN0 or AIN1, ADC inactive or channel not selected 0.01 nA
AIN2 or AIN3, ADC inactive or channel not selected 0.01
AIN0/AIN1 Resistor Divider Error ADC_CHSEL = 4 or 5, not including ADC offset/gain error ±2 LSb
Full-Scale Voltage VFS ADC code = 0x3FF 1.2 V
Bandgap Temperature Coefficient VTEMPCO From +25°C to +105°C 15 ppm
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Electrical Characteristics—SPI

(Timing specifications are guaranteed by design and not production tested.)

MASTER MODE
SPI Master Operating Frequency fMCK fMCK(MAX) = fSYS_CLK/2 60 MHz
SPI Master SCK Period tMCK 1/fMCK ns
SCK Output Pulse-Width High/Low tMCH, tMCL tMCK/2 ns
MOSI Output Hold Time After SCK Sample Edge tMOH tMCK/2 ns
MOSI Output Valid to Sample Edge tMOV tMCK/2 ns
MISO Input Valid to SCK Sample Edge Setup tMIS 5 ns
MISO Input to SCK Sample Edge Hold tMIH tMCK/2 ns
SLAVE MODE
SPI Slave Operating Frequency fSCK 48 MHz
SPI Slave SCK Period tSCK 1/fSCK ns
SCK Input Pulse-Width High/Low tSCH, tSCL tSCK/2
SSx Active to First Shift Edge tSSE 10 ns
MOSI Input to SCK Sample Edge Rise/Fall Setup tSIS 5 ns
MOSI Input from SCK Sample Edge Transition Hold tSIH 1 ns
MISO Output Valid After SCLK Shift Edge Transition tSOV 5 ns
SCK Inactive to SSx Inactive tSSD 10 ns
SSx Inactive Time tSSH 1/fSCK μs
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Electrical Characteristics—I2C

(Timing specifications are guaranteed by design and not production tested.)

STANDARD MODE
Output Fall Time tOF Standard mode, from VIH(MIN) to VIL(MAX) 150 ns
SCL Clock Frequency fSCL 0 100 kHz
Low Period SCL Clock tLOW 4.7 μs
High Time SCL Clock tHIGH 4.0 μs
Setup Time for Repeated Start Condition tSU;STA 4.7 μs
Hold Time for Repeated Start Condition tHD;STA 4.0 μs
Data Setup Time tSU;DAT 300 ns
Data Hold Time tHD;DAT 10 ns
Rise Time for SDA and SCL tR 800 ns
Fall Time for SDA and SCL tF 200 ns
Setup Time for a Stop Condition tSU;STO 4.0 μs
Bus Free Time Between a Stop and Start Condition tBUS 4.7 μs
Data Valid Time tVD;DAT 3.45 μs
Data Valid Acknowledge Time tVD;ACK 3.45 μs
FAST MODE
Output Fall Time tOF From VIH(MIN) to VIL(MAX) 150 ns
Pulse Width Suppressed by Input Filter tSP 75 ns
SCL Clock Frequency fSCL 0 400 kHz
Low Period SCL Clock tLOW 1.3 μs
High Time SCL Clock tHIGH 0.6 μs
Setup Time for Repeated Start Condition tSU;STA 0.6 μs
Hold Time for Repeated Start Condition tHD;STA 0.6 μs
Data Setup Time tSU;DAT 125 ns
Data Hold Time tHD;DAT 10 ns
Rise Time for SDA and SCL tR 30 ns
Fall Time for SDA and SCL tF 30 ns
Setup Time for a Stop Condition tSU;STO 0.6 μs
Bus Free Time Between a Stop and Start Condition tBUS 1.3 μs
Data Valid Time tVD;DAT 0.9 μs
Data Valid Acknowledge Time tVD;ACK 0.9 μs
FAST MODE PLUS
Output Fall Time tOF From VIH(MIN) to VIL(MAX) 80 ns
Pulse Width Suppressed by Input Filter tSP 75 ns
SCL Clock Frequency fSCL 0 1000 kHz
Low Period SCL Clock tLOW 0.5 μs
High Time SCL Clock tHIGH 0.26 μs
Setup Time for Repeated Start Condition tSU;STA 0.26 μs
Hold Time for Repeated Start Condition tHD;STA 0.26 μs
Data Setup Time tSU;DAT 50 ns
Data Hold Time tHD;DAT 10 ns
Rise Time for SDA and SCL tR 50 ns
Fall Time for SDA and SCL tF 30 ns
Setup Time for a Stop Condition tSU;STO 0.26 μs
Bus Free Time Between a Stop and Start Condition tBUS 0.5
  		μs
Data Valid Time tVD;DAT 0.45 μs
Data Valid Acknowledge Time tVD;ACK 0.45 μs
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Electrical Characteristics—I2S Slave

(Timing specifications are guaranteed by design and not production tested., TA = -40°C to +105°C)

Bit Clock Frequency fBCLK 96kHz LRCLK frequency 3.072 MHz
BCLK High Time tWBCLKH 0.5 1/fBCLK
BCLK Low Time 0.5 1/fBCLK
LRCLK Setup Time tLRCLK_BLCK 25 ns
Delay Time, BCLK to SD (Output) Valid tBCLK_SDO 12 ns
Setup Time for SD (Input) tSU_SDI 6 ns
Hold Time SD (Input) tHD_SDI 3 ns
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Electrical Characteristics—SD/SDIO/SDHC/MMC

(TA = -40°C to +105°C)

Clock Frequency in Data Transfer Mode fSDHC_CLK 0 fHSCLK/2 MHz
Clock Period tCLK 1/fSDHC_CLK ns
Clock Low Time tWCL 7 ns
Clock High Time tWCH 7 ns
Input Setup Time tISU 5 ns
Input Hold Time tIHLD 1 ns
Output Valid Time tOVLD 5 ns
Output Hold Time tOHLD 6 ns
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Electrical Characteristics—HyperBus

(Timing specifications are guaranteed by design and not production tested.)

HYP_CLK, HYP_CLKN Frequency fHYP_CLK 60 MHz
HYP_CLK, HYP_CLKN Period tHYP_CLK 1/fHYP_CLK ns
HYP_CLK, HYP_CLKN High Time tWHCKH 7 ns
HYP_CLK, HYP_CLKN Low Time tWHCKL 7 ns
CS Setup to RWDS tCSSU 6 ns
RWDS Setup to CK tRWDS_CK 10 ns
Dx Output Setup tOSU 5 ns
Dx Output Hold tOH 3 ns
CS Hold After CK Falling Edge tCSH 5 ns
CS High Between Transactions tCHSI 15 ns
Dx Input Setup to RWDS tISU 4 ns
Dx Input Hold tIHD 2 ns
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Electrical Characteristics—1-Wire Master

(Timing specifications are guaranteed by design and not production tested.)

Write 0 Low Time tW0L Standard 60 μs
Overdrive 8
Write 1 Low Time tW1L Standard 6 μs
Standard, Long Line mode 8
Overdrive 1
Presence Detect Sample tMSP Standard 70 μs
Standard, Long Line mode 85
Overdrive 9
Read Data Value tMSR Standard 15 μs
Standard, Long Line mode 24
Overdrive 3
Recovery Time tREC0 Standard 10 μs
Standard, Long Line mode 20
Overdrive 4
Reset Time High tRSTH Standard 480 μs
Overdrive 58
Reset Time Low tRSTL Standard 600 μs
Overdrive 70
Time Slot tSLOT Standard 70 μs
Overdrive 12
Figure 1. SPI Master Mode Timing Diagram
Figure 2. SPI Slave Mode Timing Diagram
 
Figure 3. I2C Timing Diagram
   
Figure 4. I2S Timing Diagram
 
Figure 5. SD/SDIO/SDHC/MMC Timing Diagram

 
 
Figure 6. HyperBus/Xccela Bus Timing Diagram
Figure 7. 1-Wire Master Data Timing Diagram