Detailed Description

The MAX32650–MAX32652 are low-power, mixed-signal microcontrollers based on the Arm Cortex-M4 with FPU CPU, operating at a maximum frequency of 120MHz. The devices feature five powerful and flexible power modes. A SmartDMA performs complex background processing on data being transferred, from simple arithmetic to multiply/accumulate, while the CPU is off. This function dramatically reduces overall power consumption compared to conventional solutions. This allows, for example, an external display to be refreshed while most of the chip is powered off. Built-in dynamic clock gating and firmware-controlled power gating allows the user to optimize power for the specific application.

Application code executes from an onboard 3MB program flash memory, with 1MB SRAM available for general application use. A 16KB cache improves execution throughput. Additionally, a SPI execute in place (XIP) external memory interface allows application code and data (up to 128MB) to be accessed from an external SPI flash and/or SRAM memory device.

A 10-bit delta-sigma ADC is provided with a multiplexer front end for four external input channels (two of which are 5V tolerant) and six internal power supply monitoring channels. Dedicated divided supply input channels allow direct monitoring of internal power supply voltages by the ADC. Built-in limit monitors allow converted input samples to be compared against user-configurable high and low limits, with an option to trigger an interrupt and wake the CPU from a low-power mode if attention is required.

A wide variety of communications and interface peripherals are provided, including a Hi-Speed USB 2.0 device interface, three master/slave SPI interfaces, one QuadSPI master/slave interface, three UART interfaces with flow control support, two master/slave I²C interfaces, I²S bidirectional slave interface. A Cypress Spansion HyperBus interface and a Xccela bus interface provides support for HyperFlash, HyperRAM, and Xccela PSRAM operating up to 120MB/s throughput with access up to 512MB. A SD/SDIO/MMC interface running up to 60MB/s supporting media file storage. A 24-bit TFT LCD controller provides color and monochrome display support.

The MAX32651 is a secure version of the MAX32650. It provides a trust protection unit (TPU) with encryption and advanced security features. These features include a modular arithmetic accelerator (MAA) for fast ECDSA and RSA-4096 computation. A hardware AES engine uses 128/192/256-bit keys. A memory decryption integrity unit (MDIU) provides on-the-fly code or data decryption stored in external flash. A hardware TRNG and a hardware SHA-256 HASH function are also provided. A secure bootloader authenticates applications before they are allowed to execute and update firmware with confidentiality.

The MAX32652 is a high-density, 0.35mm pitch, 140-bump WLP targeted for tiny form factor products that require high I/O counts.

The Arm Cortex-M4 with FPU combines high-efficiency signal processing functionality with flexible low-power operating modes. The features of this implementation of the familiar Arm Cortex-M4 architecture include:

• Floating point unit (FPU)
• Memory protection unit
• Multilayer, 32-bit AHB matrix
• Full debug support level
  • Debug access port (DAP)
  • Breakpoints
  • Flash patch
  • Halting debug
  • Development and debug interface
• NVIC support
  • Programmable IRQ generation for each interrupt source
  • Unique vectors for each interrupt channel
  • 8 programmable priority levels support nesting and preemption
  • External GPIO interrupts grouped by GPIO port
• DSP supports single instruction multiple data (SIMD) path DSP extensions, providing:
  • 4 parallel 8-bit add/sub
  • 2 parallel 16-bit add/sub
  • 2 parallel MACs
  • 32- or 64-bit accumulate
  • Signed, unsigned, data with or without saturation

3MB of internal flash memory provides nonvolatile storage of program and data memory.

Flash can be expanded through the SPIXF flash serial interface backed by 16KB of cache. The SPIXF flash interface can address an additional 128MB.

The internal 1MB SRAM provides low-power retention of application information in all power modes except shutdown. The SRAM can be divided into granular banks that create a flexible SRAM retention architecture. This data retention feature is optional and configurable. This granularity allows the application to minimize its power consumption by only retaining the most essential data.

SRAM can be expanded through the SPIXR SRAM serial interface backed by 16KB of cache. The SPIXR SRAM interface can address an additional 512MB.

The secure digital interface (SDI) provides high-speed, high-density data storage capability for media files and large long-term data logs. This interface supports eMMC, SD, SDHC, and SDXC memory devices at transfer rates up to 60MB/s. The 7-pin interface (4 data, 1 clock, 1 command, 1 write-protect) supports the following specifications:

• SD Host Controller Standard Specification Version 3.00

• SDIO Card Specification Version 3.0

• SD Memory Card Specification Version 3.01

• SD Memory Card Security Specification Version 1.01

• MMC Specification Version 4.51

The Spansion HyperBus/Xccela bus interface provides access to external Cypress Spansion HyperBus and Xccela bus memory products both SRAM and/or flash. This interface provides a means of high-speed execution from external SRAM or flash allowing system expansion when internal memory resources are insufficient. Up to 512MB SRAM or 512MB flash at a speed of up to 60MHz or 120MB/s is supported. It is a high-speed low-pin count interface that is memory-mapped into the CPU memory space making access to this external memory as easy as accessing on-chip RAM. Data is transferred over a high-speed, 8-bit bus. Slave memory devices are selected with two chip selects. HyperBus transfers are clocked using a differential clock while Xccela bus transfers use a single-ended clock. This interface supports 1.8V operation only.

Features of the HyperBus/Xccela bus interface include:

• Master/slave system
• 120MB/s maximum data transfer rate
• Double data rate (DDR): two data transfers per clock cycle
• Transparent bus operation to the processor
• 16KB write-through cache
• Two chip selects for two memory ports
  • Each port supports memories up to 512MB
• Addresses two external memories, one at a time
• Interfaces to HyperFlash, HyperRAM, and Xccela PSRAM
• Zero wait state burst mode operation
• Low-power half sleep mode
  • Puts the external memory device into low-power mode while retaining memory contents
• Configurable timing parameters

The high-frequency oscillator operates at a maximum frequency of 120MHz.

Optionally, four other oscillators can be selected depending upon power needs:

• 50MHz low-power oscillator
• 8kHz nanoring oscillator
• 32.768kHz oscillator (external crystal required)
• 7.3728MHz oscillator

This clock is the primary clock source for the digital logic and peripherals. Select the 7.3728MHz internal oscillator to optimize active power consumption. Using the 7.3727MHz oscillator allows UART communications to meet a ±2% baud rate tolerance.

Wake-up is possible from either the 7.3728MHz internal oscillator or the high-frequency oscillator. The device exits power-on reset using the the 50MHz oscillator.

An external 32.768kHz timebase is required when using the RTC.

Most general-purpose I/O (GPIO) pins share both a firmware-controlled I/O function and one or more special function signals associated with peripheral modules. Pins can be individually enabled for GPIO or peripheral special function use. Configuring a pin as a special function usually supersedes its use as a firmware-controlled I/O. Though this multiplexing between peripheral and GPIO functions is usually static, it can also be done dynamically. The electrical characteristics of a GPIO pin are identical whether the pin is configured as an I/O or special function, except where explicitly noted in the electrical characteristics tables.

In GPIO mode, pins are logically divided into ports of 32 pins. Each pin of a port has an interrupt function that can be independently enabled, and configured as a level- or edge-sensitive interrupt. All GPIOs of a given port share the same interrupt vector. Some packages do not have all of the GPIOs available.

When configured as GPIO, the following features are provided. The features can be independently enabled or disabled on a per-pin basis.

• Configurable as input, output, bidirectional, or high impedance
• Optional internal pullup resistor or internal pulldown resistor when configured as input
• Exit from low-power modes on rising or falling edge
• Selectable standard- or high-drive modes

The MAX32650–MAX32652 provides up to 105 GPIO (140 WLP), 97 GPIO (144 TQFP), and 67 GPIO (96 WLP).

GPIOs, which have any HyperBus alternate functionality (P1.[21:18], P1.[16:11], P3.0), can only be used with the V_DDIO supply, whether used as a GPIO or any alternate function.

The Standard DMA (direct memory access) controller provides a means to off-load the CPU for memory/peripheral data transfer leading to a more power-efficient system. It allows automatic one-way data transfer between two entities. These entities can be either memories or peripherals. The transfers are done without using CPU resources.

The following transfer modes are supported:

• 16 channel
• Peripheral to data memory
• Data memory to peripheral
• Data memory to data memory
• Event support

All DMA transactions consist of an AHB burst read into the DMA FIFO followed immediately by an AHB burst write from the FIFO.

The SmartDMA controller provides low-power memory/peripheral access control that can run data collection tasks and perform complex background processing on data being transferred, from simple arithmetic to multiply/accumulate, while the CPU is off, significantly reducing power consumption (Background mode). The SmartDMA controller allows peripherals on the AHB to access main system memory (SRAM) independent of the CPU. It is configured through the APB and can configure itself through the AHB-to-APB bridge. The SmartDMA engine runs code from system SRAM. If desired, custom SmartDMA algorithms supporting data post-processing can be developed by the user.

Key features:

• Dedicated 32-bit controller with general-purpose timer
• APB read access to the SmartDMA registers
• Configurable start IP address
• Selects 32 interrupts from peripherals from a total of 80 available interrupts to initiate DMA operations
• Global enable (SDMA_EN) keeps SmartDMA in reset except APB interface
• Synchronous interrupt output to CPU

The 10-bit delta-sigma ADC provides an integrated reference generator and a single-ended input multiplexer. The multiplexer selects an input channel from either the external analog input signals (AIN0, AIN1, AIN2, and AIN3) or the internal power supply inputs. AIN0 and AIN1 are 5V tolerant, making them suitable for monitoring batteries. An internal 1.22V bandgap or the V_DDA analog supply can be chosen as the ADC reference.

An optional feature allows samples captured by the ADC to be automatically compared against user-programmable high and low limits. Up to four channel limit pairs can be configured in this way. The comparison allows the ADC to trigger an interrupt (and potentially wake the CPU from a low-power sleep mode) when a captured sample goes outside the preprogrammed limit range. Since this comparison is performed directly by the sample limit monitors, it can be performed even while the main CPU is suspended in a low-power mode.

​The ADC measures:

• AIN[3:2] (up to 3.3V)
• AIN[1:0] (up to 5.5V)
• V_CORE
• V_DD18
• V_DDB
• V_RTC
• V_DDIO
• V_DDIOH

The power management unit (PMU) provides high-performance operation while minimizing power consumption. It exercises intelligent, precise control of power distribution to the CPU and peripheral circuitry.

The PMU provides the following features:

• User-configurable system clock
• Automatic enabling and disabling of crystal oscillators based on power mode
• Multiple clock domains
• Fast wake-up of powered-down peripherals when activity detected

This mode corresponds to the Arm Cortex-M4 with FPU Deep-Sleep mode. In this mode, the register settings and all volatile memory is preserved. The GPIO pins retain their state in this mode. The transition from Deep-Sleep to Active mode is faster than the transition from Backup mode because system initialization is not required.

The high-speed oscillator that generates the 120MHz system clock can be shut down to provide additional power savings over Sleep or Background modes.

There are four sources from which Background mode can be exited to return to Active mode: RTC interrupt, GPIO interrupt, USB interrupt, or RSTN assertion.

This mode places the CPU in a static, low-power state that supports a fast wake-up to Active mode feature. In Backup mode, all of the SRAM can be retained with restrictions depending upon which supply is used to support this mode. Data retention in this mode can be maintained using only the V_CORE or V_RTC supplies. Optionally, the V_CORE voltage input can be turned off at its source and an internal retention regulator can be enabled to power the state so that the V_RTC voltage input is all that is required for mode operation including the RTC.

If the V_RTC supply is used, then either 32KB or 96KB of SRAM can be retained and all GPIO can be retained. If the V_CORE supply is subsequently turned on then the power mode will wake to the Active state.

If the V_CORE supply is used, then either 32KB, 96KB, or 1024KB of SRAM can be retained and all GPIO can be retained.

There are four sources from which Background mode can be exited to return to Active mode: RTC interrupt, GPIO interrupt, USB interrupt, or RSTN assertion.

A real-time clock (RTC) keeps the time of day in absolute seconds. The 32-bit seconds register can count up to approximately 136 years and be translated to calendar format by application software.

The RTC provides a time-of-day alarm that can be programmed to any future value between 1 second and 12 days. When configured for long intervals, the time-of-day alarm can be used as a power-saving timer, allowing the device to remain in an extremely low-power mode but still awaken periodically to perform assigned tasks. A second independent 32-bit 1/4096 subsecond alarm can be programmed between 244μs and 1s. Both can be configured as recurring alarms. When enabled, either alarm can cause an interrupt or wake the device from most low-power modes.

The time base is generated by a 32.768kHz crystal or an external clock source that must meet the electrical/timing requirements in the Electrical Characteristics table.

The RTC calibration feature provides the ability for user-software to compensate for minor variations in the RTC oscillator, crystal, temperature, and board layout. Enabling the 32KCAL alternate function outputs a timing signal derived from the RTC. External hardware can measure the frequency and adjust the RTC frequency in increments of ±127ppm with 1ppm resolution. Under most circumstances, the oscillator does not require any calibration.

A cyclic redundancy check (CRC) hardware module provides fast calculations and data integrity checks by application software. The CRC module supports the following polynomials:

• CRC-16-CCITT
• CRC-32 (X³² + X²⁶ + X²³ + X²² + X¹⁶ + X¹² + X¹¹ + X¹⁰ + X⁸ + X⁷ + X⁵ + X⁴ + X² + X + 1)

General-purpose, 32-bit timers provide timing, capture/compare, or generation of pulse-width modulated (PWM) signals with minimal software interaction.

The timer provides the following features:

• 32-bit up/down autoreload
• Programmable prescaler
• PWM output generation
• Capture, compare, and capture/compare capability
• External pin multiplexed with GPIO for timer input, clock gating or capture
• Timer output pin
• Timer interrupt

The MAX32650–MAX32652 provides six instances of the general-purpose 32-bit timer (TMR0–TMR5).

Multiple, independent pulse train generators can provide either a square wave or a repeating pattern from 2 to 32 bits in length. Any single pulse train generator or any desired group of pulse train generators can be synchronized at the bit level allowing for multibit patterns. Each pulse train generator is independently configurable.

The pulse train generators provide the following features:

• Independently enabled
• Safe enable and disable for pulse trains without bit banding
• Multiple pin configurations allow for flexible layout
• Pulse trains can be started/synchronized independently or as a group
• Frequency of each enabled pulse train generator is also set separately, based on a divide down (divide by 2, divide by 4, divide by 8, and so on) of the input pulse train module clock
• Multiple repetition options
  • Single shot (nonrepeating pattern of 2 to 32 bits)
  • Pattern repeats user-configurable number of times or indefinitely
  • Termination of one pulse train loop count can restart one or more other pulse trains

The pulse train engine feature is an alternate function associated with a GPIO pin. In most cases, enabling the pulse train engine function supersedes the GPIO function.

The MAX32650–MAX32652 provide up to 16 instances of the pulse train engine peripheral (PT[15:0]).

The serial peripheral interface (SPI) is a highly configurable, flexible, and efficient synchronous interface between multiple SPI devices on a single bus. The bus uses a single clock signal and multiple data signals, and one or more slave select lines to address only the intended target device. The SPI operates independently and requires minimal processor overhead.

The provided SPI peripherals can operate in either slave or master mode and provide the following features:

• SPI modes 0, 1, 2, 3 for single-bit communication
• 3- or 4-wire mode for single-bit slave device communication
• Full-duplex operation in single-bit, 4-wire mode
• Dual and quad data modes supported
• Multiple slave select lines on some instances
• Multimaster mode fault detection
• Programmable interface timing
• Programmable SCK frequency and duty cycle
• 32-byte transmit and receive FIFOs
• Slave select assertion and deassertion timing with respect to leading/trailing SCK edge

The MAX32650–MAX32652 provide four instances of the SPI peripheral (SPI0, SPI1 and SPI2, SPI3) in accordance with the specifications shown in Table 1:

The I²S interface is a bidirectional, three-wire serial bus that provides serial communications for codecs and audio amplifiers compliant with the I²S Bus Specification, June 5, 1996. It provides the following features:

• Slave mode operation
• Normal and left-justified data alignment
• 16-bit audio transfer
• Wake-up on FIFO status (full/empty/threshold)
• Interrupts generated for FIFO status​
• Receiver FIFO depth of 32 bytes
• Transmitter FIFO depth of 32 bytes

The MAX32650–MAX32652 provide one instance of the I²S peripheral that is multiplexed with the SPI2 peripheral.

The integrated USB device controller is compliant with the Hi-Speed (480Mbps) USB 2.0 specification. The integrated USB physical interface (PHY) reduces board space and system cost. An integrated voltage regulator enables smart switching between the main supply and V_DDB when connected to a USB host controller.

• Supports DMA for the endpoint buffers. A total of 12 endpoint buffers are supported with configurable selection of IN or OUT in addition to endpoint 0.
• Isochronous, bulk, interrupt, and control transfers
• Automatic packet splitting and combining
• FIFOs up to 4096 bytes deep
• Double packet buffering
• USB 2.0 test mode support

The I²C interface is a bidirectional, two-wire serial bus that provides a medium-speed communications network. It can operate as a one-to-one, one-to-many or many-to-many communications medium. Two I²C master/slave interface to a wide variety of I²C-compatible peripherals. These engines support standard mode, fast mode, and fast mode plus I²C speeds. It provides the following features:

• Master or slave mode operation
• Supports standard 7-bit addressing or 10-bit addressing
• RESTART condition
• Interactive Receive mode
• Tx FIFO Preloading
• Support for clock stretching to allow slower slave devices to operate on higher speed busses
• Multiple transfer rates
  • Standard mode: 100kbps
  • Fast mode: 400kbps
  • Fast mode plus: 1000kbps
• Internal filter to reject noise spikes
• Receiver FIFO depth of 8 bytes
• Transmitter FIFO depth of 8 bytes

The MAX32650–MAX32652 provide two instances of the I²C peripheral (I2C0 and I2C1).

The universal asynchronous receiver-transmitter (UART) interface supports full-duplex asynchronous communication with optional hardware flow control (HFC) modes to prevent data overruns. If HFC mode is enabled on a given port, the system uses two extra pins to implement the industry standard request to send (RTS) and clear to send (CTS) flow control signaling. Each UART is individually programmable.

• 2-wire interface or 4-wire interface with flow control
• 32-byte send/receive FIFO
• Full-duplex operation for asynchronous data transfers
• Interrupts available for frame error, parity error, CTS, RX FIFO overrun and FIFO full/partially full conditions
• Automatic parity and frame error detection
• Independent baud-rate generator
• Programmable 9th bit parity support
• Multidrop support
• Start/stop bit support
• Hardware flow control using RTS/CTS
• Baud rate generation with ±2% optionally utilizing the 7.3727MHz oscillator baud rate clock
• Maximum baud rate 4000kB
• Two DMA channels can be connected (read and write FIFOs)
• Programmable word size (5 bits to 8 bits)

The MAX32650–MAX32652 provide three instances of the UART peripheral (UART0, UART1, and UART2) according to the specifications in Table 2:

There are two SPI execute-in-place master interfaces. One for SRAM (SPIXR) and one for flash (SPIXF) with dedicated slave selects. This feature allows the CPU to transparently execute instructions stored in an external SPI memory device. Instructions fetched through the SPI master are cached just like instructions fetched from internal program memory. The SPI SRAM master provides write-back capability. These two SPI execute in place master interfaces can also be used to access large amounts of external static data that would otherwise reside in internal data memory.

Maxim's 1-Wire bus consists of a single line to provide both power and data communications and a ground return. The bus supports a serial, multidrop communication protocol between a master and one or more slave devices with the minimum amount of interconnection.

Maxim's 1-Wire bus consists of one signal that carries data and also supplies power to the slave devices, and a ground return. The bus master communicates serially with one or more slave devices through the bidirectional, multidrop 1-Wire bus. The single contact serial interface is ideal for communication networks requiring minimal interconnection.

The provided 1-Wire master supports the following features:

• Single contact for control and operation
• Unique factory identifier for any 1-Wire device
• Multiple device capability on a single line

The MAX32650–MAX32652 1-Wire master supports both the standard (15.6kbps) and overdrive (110kbps) speeds.

The 24-bit color TFT controller is controlled by the CPU through the APB and fed graphic data through the AHB. The controller supports the following display types:

• Active matrix TFT panels with up to 24-bit bus interface
• Single/dual-panel monochrome STN panels (4-bit and 8-bit bus interfaces)
• Single/dual-panel color STN panels, 8-bit bus interface
• TFT panels up to 24 bpp, direct 8:8:8 RG
• Color STN panels up to 16bpp, direct 5:5:5 with one bit not being used
• Mono STN panels up to 4bpp, pelletized, 16 gray scales selected from 16

The controller can be programmed to operate a wide range of panel resolutions (including but not limited to the following settings):

• 320 x 200, 320 x 240
• 640 x 200, 640 x 240, 640 x 480
• 800 x 600
• 1024 x 768
• 2048 x 2048
• 4096 x 4096

Special versions of the device are available with a serial wire debug or JTAG interface that is used only during application development and debugging. The interface is used for code loading, ICE debug activities, and control of boundary scan activities.

Random numbers are a vital part of a secure application, providing random numbers that can be used for cryptographic seeds or strong encryption keys to ensure data privacy.

Software can use random numbers to trigger asynchronous events that result in nondeterministic behavior. This is helpful in thwarting replay attacks or key search approaches. An effective true random number generator (TRNG) must be continuously updated by a high-entropy source.

The provided TRNG is continuously driven by a physically-unpredictable entropy source. It generates a 128-bit true random number in 128 system clock cycles.

The TRNG can support the system-level validation of many security standards such as FIPS 140-2, PCI-PED, and Common Criteria. Contact Maxim for details of compliance with specific standards.

The provided high-speed, hardware-based modulo arithmetic accelerator (MAA) performs mathematical computations that support strong cryptographic algorithms. These include: 

• 2048-bit DSA
• 4096-bit RSA
• Elliptic curve public key infrastructure

The dedicated hardware-based AES engine supports the following algorithms:

• AES-128
• AES-192
• AES-256

The AES keys are automatically generated by the engine and stored in dedicated flash to protect against tampering. Key generation and storage is transparent to the user.

SHA-256 is a cryptographic hash function part of the SHA-2 family of algorithms. It authenticates user data and verifies its integrity. It is used for digital signatures.

The device provides a hardware SHA-256 engine for fast computation of 256-bit digests.

The root of trust starts with trusted software and the microcontroller's TPU. Communications between a host and the device must be secure and authenticated, and program integrity must be verified each time before execution to ensure the trustworthiness of device.

The device's root of trust is based on a Maxim Integrated master root verification key and a signed customer verification key (CVK). Customers submit their public CVK to Maxim Integrated, which is then signed and this public key sent back to the customer. This process is quick and required only once before the software is released for the first time and is not needed during the software development. A customer can then load their own key and download their signed binary executable code.

A life-cycle scheme allows devices to be permanently disabled to deactivate a deployed application. After the software development is complete, but before deployment, the JTAG debugger interface must be disabled in a separate step.

Communication between a host system and the device uses a system of digitally signed packets. This guarantees the integrity and authenticity of all communication before executing configuration commands and the loading or verification of program memory. One or more serial interfaces are available for communication.

This also enables the assembly and programming of the customers final product by third-party assembly houses without the required cost and complexity of ensuring that the assembly house implements and maintains a secure production facility. It also allows for in-field software upgrades to deployed products, thus eliminating the costly need to return a product to the manufacturer for any software changes.

The MAX32651 SCPBL selects the USB as the factory default interface using preprogrammed software. Performing a mass erase before executing the preprogrammed software or erasing the last page of flash memory will select UART0 as the interface. Once an SCPBL session is opened, the chosen interface must be explicitly assigned using a dedicated command SCPBL command. This allows the last page of flash memory to be erased, if needed, and used by the application software. The 96-bump WLP can only use the USB interface and must run the preprogrammed software to select USB as the factory interface.

Figure 10 depicts a flowchart of the SCP activation. It shows the actions of the device and how the SCPBL interfaces are selected.

Designers must have the following documents to use all the features of this device.

• This data sheet, which contains electrical/timing specifications, package information, and pin descriptions.
• The corresponding revision-specific errata sheet.
• The corresponding user guide, which contains detailed information and programming guidelines for core features and peripherals.