| GPIO | ALTERNATE FUNCTION 1 | ALTERNATE FUNCTION 2 |
|---|---|---|
| P0.0 | PT3 | SPIXF_SDIO2** |
| P0.1 | SPIXR_SDIO0** | ― |
| P0.2 | SPIXR_SDIO2** | ― |
| P0.3 | SPIXR_SCK** | ― |
| P0.4 | SPIXR_SDIO3** | ― |
| P0.5 | SPIXR_SDIO1** | ― |
| P0.6 | SPIXR_SS0** | ― |
| P0.7 | SPIXF_SS0** | ― |
| P0.8 | SPIXF_SCK** | ― |
| P0.9 | SPIXF_SDIO1** | ― |
| P0.10 | SPIXF_SDIO0** | ― |
| P0.11 | SPIXF_SDIO2** | ― |
| P0.12 | SPIXF_SDIO3** | ― |
| P0.13 | SPI3_SS1 | CLCD_G0 |
| P0.14 | SPI3_SS2 | CLCD_G1 |
| P0.15 | SPI3_SDIO3 | CLCD_G2 |
| P0.16 | SPI3_SCK | CLCD_G3 |
| P0.17 | SPI3_SDIO2 | CLCD_G4 |
| P0.18 | SPI3_SS3 | CLCD_G5 |
| P0.19 | SPI3_SS0 | CLCD_G6 |
| P0.20 | SPI3_SDIO1 | CLCD_G7 |
| P0.21 | SPI3_SDIO0 | — |
| P0.22 | SPI0_SS0 | CLCD_VDEN |
| P0.23 | PT15 | CLCD_CLK |
| P0.24 | RXEV | CLCD_HSYNC |
| P0.25 | TXEV | CLCD_B0 |
| P0.26 | TDI | TDI |
| P0.27 | TDO | TDO |
| P0.28 | TMS (SWDIO)†† | TMS (SWDIO)†† |
| P0.29 | TCK (SWDCLK)†† | TCK (SWDCLK)†† |
| P0.30 | — | CLCD_B0 |
| P0.31 | 32KCAL | SDHC_CDN |
| P1.0 | SDHC_CMD | SPIXF_SDIO3** |
| P1.1 | SDHC_DAT2 | SPIXF_SDIO1** |
| P1.2 | SDHC_WP | SPIXF_SS0** |
| P1.3 | SDHC_DAT3 | CLCD_CLK |
| P1.4 | SDHC_DAT0 | SPIXF_SDIO0** |
| P1.5 | SDHC_CLK | SPIXF_SCK** |
| P1.6 | SDHC_DAT1 | PT0 |
| P1.7 | UART2_CTS | PT1 |
| P1.8 | UART2_RTS | PT2 |
| P1.9 | UART2_RX | PT3 |
| P1.10 | UART2_TX | PT4 |
| P1.11 | HYP_CS0N | SPIXR_SDIO0** |
| P1.12 | HYP_D0 | SPIXR_SDIO1** |
| P1.13 | HYP_D4 | SPIXR_SS0** |
| P1.14 | HYP_RWDS | PT5 |
| P1.15 | HYP_D1 | SPIXR_SDIO2** |
| P1.16 | HYP_D5 | SPIXR_SCK** |
| P1.17 | PT9 | ― |
| P1.18 | HYP_D6 | PT6 |
| P1.19 | HYP_D2 | PT7 |
| P1.20 | HYP_D3 | CLCD_HSYNC |
| P1.21 | HYP_D7 | PT8 |
| P1.22* | ― | ― |
| P1.23 | SPI1_SS0 | CLCD_B1 |
| P1.24 | SPI1_SS2 | CLCD_B2 |
| P1.25 | SPI1_SS1 | CLCD_B3 |
| P1.26 | SPI1_SCK | CLCD_B4 |
| P1.27 | SPI1_SS3 | CLCD_B5 |
| P1.28 | SPI1_MISO | CLCD_B6 |
| P1.29 | SPI1_MOSI | CLCD_B7 |
| P1.30 | OWM_PUPEN | CLCD_R0 |
| P1.31 | OWM_IO | CLCD_R1 |
| P2.0 | SPI2_SS2 | PT9 |
| P2.1 | SPI2_SS1 | PT10 |
| P2.2 | SPI2_SCK (I2S_BCLK)† | CLCD_LEND |
| P2.3 | SPI2_MISO (I2S_SDI)† | CLCD_PWREN |
| P2.4 | SPI2_MOSI (I2S_SDO)† | ― |
| P2.5 | SPI2_SS0 (I2S_LRCLK)† | PT11 |
| P2.6 | SPI2_SS3 | CLCD_VSYNC |
| P2.7 | I2C0_SDA | ― |
| P2.8 | I2C0_SCL | ― |
| P2.9 | UART0_CTS | PT12 |
| P2.10 | UART0_RTS | PT14 |
| P2.11 | UART0_RX | PT13 |
| P2.12 | UART0_TX | PT15 |
| P2.13 | UART1_CTS | CLCD_R2 |
| P2.14 | UART1_RX | CLCD_R3 |
| P2.15 | UART1_RTS | CLCD_R4 |
| P2.16 | UART1_TX | CLCD_R5 |
| P2.17 | I2C1_SDA | CLCD_R6 |
| P2.18 | I2C1_SCL. This device pin also has a special function associated with the Secure Communications Protocol Bootloader. See Table 3 for details. | CLCD_R7. This device pin also has a special function associated with the Secure Communications Protocol Bootloader. See Table 3 for details. |
| P2.19 | PT4 | ― |
| P2.20 | PT5 | ― |
| P2.21 | PT7 | ― |
| P2.22 | PT8 | ― |
| P2.23 | PT6 | SPIXR_SDIO3** |
| P2.24 | PT10 | ― |
| P2.25 | PT11 | ― |
| P2.26 | PT12 | ― |
| P2.27 | PT13 | ― |
| P2.28 | PT14.This device pin also has a special function associated with the Secure Communications Protocol Bootloader. See Table 3 for details. | This device pin also has a special function associated with the Secure Communications Protocol Bootloader. See Table 3 for details. |
| P2.29 | PT0 | ― |
| P2.30 | PT1 | ― |
| P2.31 | PT2 | ― |
| P3.0 | PDOWN††† | HYP_CS1N |
| P3.1 | SPI0_MISO | ― |
| P3.2 | SPI0_MOSI | ― |
| P3.3 | SPI0_SCK | ― |
| P3.4 | TMR0 | ― |
| P3.5 | TMR2 | ― |
| P3.6 | TMR4 | ― |
| P3.7 | TMR1 | ― |
| P3.8 | TMR3 | ― |
| P3.9 | TMR5 | ― |
*GPIO not pinned out.
**This signal can be mapped to more than one GPIO, but there is only one instance of this peripheral.
†I2S_BCLK, I2S_LRCLK, I2S_SDI, and I2S_SDO when enabled.
††Single-wire debug when enabled.
†††PDOWN is not operative during or immediately after reset since this function appears as an Alternate Function 1.
| GPIO | ALTERNATE FUNCTION 1 | ALTERNATE FUNCTION 2 |
|---|---|---|
| P0.0* | — | — |
| P0.1* | — | — |
| P0.2* | — | — |
| P0.3* | — | — |
| P0.4* | — | — |
| P0.5* | — | — |
| P0.6* | — | — |
| P0.7* | — | — |
| P0.8* | — | — |
| P0.9* | — | — |
| P0.10* | — | — |
| P0.11 | SPIXF_SDIO2** | P0.11 |
| P0.12* | — | — |
| P0.13 | SPI3_SS1 | CLCD_G0 |
| P0.14 | SPI3_SS2 | CLCD_G1 |
| P0.15 | SPI3_SDIO3 | CLCD_G2 |
| P0.16 | SPI3_SCK | CLCD_G3 |
| P0.17 | SPI3_SDIO2 | CLCD_G4 |
| P0.18 | SPI3_SS3 | CLCD_G5 |
| P0.19 | SPI3_SS0 | CLCD_G6 |
| P0.20 | SPI3_SDIO1 | CLCD_G7 |
| P0.21 | SPI3_SDIO0 | — |
| P0.22 | — | CLCD_VDEN |
| P0.23* | — | — |
| P0.24* | — | — |
| P0.25* | — | — |
| P0.26 | TDI | — |
| P0.27 | TDO | — |
| P0.28 | TMS (SWDIO)†† | — |
| P0.29 | TCK (SWDCLK)†† | — |
| P0.30 | — | CLCD_B0 |
| P0.31* | — | — |
| P1.0 | SDHC_CMD | SPIXF_SDIO3** |
| P1.1 | SDHC_DAT2 | SPIXF_SDIO1** |
| P1.2 | SDHC_WP | SPIXF_SS0** |
| P1.3 | SDHC_DAT3 | CLCD_CLK |
| P1.4 | SDHC_DAT0 | SPIXF_SDIO0** |
| P1.5 | SDHC_CLK | SPIXF_SCK** |
| P1.6 | SDHC_DAT1 | PT0 |
| P1.7* | — | — |
| P1.8 | UART2_RTS | PT2 |
| P1.9 | UART2_RX | PT3 |
| P1.10 | UART2_TX | PT4 |
| P1.11 | — | SPIXR_SDIO0** |
| P1.12 | — | SPIXR_SDIO1** |
| P1.13 | — | SPIXR_SS0** |
| P1.14 | — | PT5 |
| P1.15 | — | SPIXR_SDIO2** |
| P1.16 | — | SPIXR_SCK** |
| P1.17* | — | — |
| P1.18 | — | PT6 |
| P1.19 | — | PT7 |
| P1.20 | — | CLCD_HSYNC |
| P1.21 | — | PT8 |
| P1.22* | — | — |
| P1.23 | SPI1_SS0 | CLCD_B1 |
| P1.24 | SPI1_SS2 | CLCD_B2 |
| P1.25 | SPI1_SS1 | CLCD_B3 |
| P1.26 | SPI1_SCK | CLCD_B4 |
| P1.27 | SPI1_SS3 | CLCD_B5 |
| P1.28 | SPI1_MISO | CLCD_B6 |
| P1.29 | SPI1_MOSI | CLCD_B7 |
| P1.30 | OWM_PUPEN | CLCD_R0 |
| P1.31 | OWM_IO | CLCD_R1 |
| P2.0 | SPI2_SS2 | PT9 |
| P2.1* | — | — |
| P2.2 | SPI2_SCK (I2S-BCLK)† | CLCD_LEND |
| P2.3 | SPI2_MISO (I2S-SDI)† | CLCD_PWREN |
| P2.4 | SPI2_MOSI (I2S-SDO)† | — |
| P2.5 | SPI2_SS0 (I2S_LRCLK)† | PT11 |
| P2.6 | SPI2_SS3 | CLCD_VSYNC |
| P2.7* | — | — |
| P2.8* | — | — |
| P2.9 | UART0_CTS | PT12 |
| P2.10* | — | — |
| P2.11 | UART0_RX | PT13 |
| P2.12 | UART0_TX | PT15 |
| P2.13 | UART1_CTS | CLCD_R2 |
| P2.14 | UART1_RX | CLCD_R3 |
| P2.15 | UART1_RTS | CLCD_R4 |
| P2.16 | UART1_TX | CLCD_R5 |
| P2.17 | I2C1_SDA | CLCD_R6 |
| P2.18 | I2C1_SCL. This device pin also has a special function associated with the Secure Communications Protocol Bootloader. See Table 3 for details. | CLCD_R7. This device pin also has a special function associated with the Secure Communications Protocol Bootloader. See Table 3 for details. |
| P2.19* | — | — |
| P2.20* | — | — |
| P2.21* | — | — |
| P2.22* | — | — |
| P2.23 | PT6 | SPIXR_SDIO3** |
| P2.24* | — | — |
| P2.25* | — | — |
| P2.26* | — | — |
| P2.27* | — | — |
| P2.28* | — | — |
| P2.29* | — | — |
| P2.30* | — | — |
| P2.31* | — | — |
| P3.0* | — | — |
| P3.1* | — | — |
| P3.2* | — | — |
| P3.3* | — | — |
| P3.4 | TMR0 | — |
| P3.5 | TMR2 | — |
| P3.6 | TMR4 | — |
| P3.7 | TMR1 | — |
| P3.8 | TMR3 | — |
| P3.9 | TMR5 | — |
*GPIO not pinned out.
**This signal can be mapped to more than one GPIO, but there is only one instance of this peripheral.
†I2S_BCLK, I2S_LRCLK, I2S_SDI, I2S_SDO when enabled.
††Single-wire debug when enabled.
| GPIO | ALTERNATE FUNCTION 1 | ALTERNATE FUNCTION 2 |
|---|---|---|
| P0.0* | — | — |
| P0.1 | SPIXR_SDIO0** | — |
| P0.2 | SPIXR_SDIO2** | — |
| P0.3 | SPIXR_SCK** | — |
| P0.4 | SPIXR_SDIO3** | — |
| P0.5 | SPIXR_SDIO1** | — |
| P0.6 | SPIXR_SS0** | — |
| P0.7 | SPIXF_SS0** | — |
| P0.8 | SPIXF_SCK** | — |
| P0.9 | SPIXF_SDIO1** | — |
| P0.10 | SPIXF_SDIO0** | — |
| P0.11 | SPIXF_SDIO2** | — |
| P0.12 | SPIXF_SDIO3** | — |
| P0.13 | SPI3_SS1 | CLCD_G0 |
| P0.14 | SPI3_SS2 | CLCD_G1 |
| P0.15 | SPI3_SDIO3 | CLCD_G2 |
| P0.16 | SPI3_SCK | CLCD_G3 |
| P0.17 | SPI3_SDIO2 | CLCD_G4 |
| P0.18 | SPI3_SS3 | CLCD_G5 |
| P0.19 | SPI3_SS0 | CLCD_G6 |
| P0.20 | SPI3_SDIO1 | CLCD_G7 |
| P0.21 | SPI3_SDIO0 | — |
| P0.22 | SPI0_SS0 | CLCD_VDEN |
| P0.23 | PT15 | CLCD_CLK |
| P0.24 | RXEV | CLCD_HSYNC |
| P0.25 | TXEV | CLCD_B0 |
| P0.26 | TDI | — |
| P0.27 | TDO | — |
| P0.28 | TMS (SWDIO)††† | — |
| P0.29 | TCK (SWDCLK)††† | — |
| P0.30 | — | CLCD_B0 |
| P0.31 | 32KCAL | SDHC_CDN |
| P1.0 | SDHC_CMD | SPIXF_SDIO3** |
| P1.1 | SDHC_DAT2 | SPIXF_SDIO1** |
| P1.2 | SDHC_WP | SPIXF_SS0** |
| P1.3 | SDHC_DAT3 | CLCD_CLK |
| P1.4 | SDHC_DAT0 | SPIXF_SDIO0** |
| P1.5 | SDHC_CLK | SPIXF_SCK** |
| P1.6 | SDHC_DAT1 | PT0 |
| P1.7 | UART2_CTS | PT1 |
| P1.8 | UART2_RTS | PT2 |
| P1.9 | UART2_RX | PT3 |
| P1.10 | UART2_TX | PT4 |
| P1.11 | HYP_CS0N | SPIXR_SDIO0** |
| P1.12 | HYP_D0 | SPIXR_SDIO1** |
| P1.13 | HYP_D4 | SPIXR_SS0** |
| P1.14 | HYP_RWDS | PT5 |
| P1.15 | HYP_D1 | SPIXR_SDIO2** |
| P1.16 | HYP_D5 | SPIXR_SCK** |
| P1.17 | PT9 | - |
| P1.18 | HYP_D6 | PT6 |
| P1.19 | HYP_D2 | PT7 |
| P1.20 | HYP_D3 | CLCD_HSYNC |
| P1.21 | HYP_D7 | PT8 |
| P1.22 | — | — |
| P1.23 | SPI1_SS0 | CLCD_B1 |
| P1.24 | SPI1_SS2 | CLCD_B2 |
| P1.25 | SPI1_SS1 | CLCD_B3 |
| P1.26 | SPI1_SCK | CLCD_B4 |
| P1.27 | SPI1_SS3 | CLCD_B5 |
| P1.28 | SPI1_MISO | CLCD_B6 |
| P1.29 | SPI1_MOSI | CLCD_B7 |
| P1.30 | OWM_PUPEN | CLCD_R0 |
| P1.31 | OWM_IO | CLCD_R1 |
| P2.0 | SPI2_SS2 | PT9 |
| P2.1 | SPI2_SS1 | PT10 |
| P2.2 | SPI2_SCK (I2S-BCLK)† | CLCD_LEND |
| P2.3 | SPI2_MISO (I2S-SDI)† | CLCD_PWREN |
| P2.4 | SPI2_MOSI (I2S-SDO)† | — |
| P2.5 | SPI2_SS0 (I2S_LRCLK)† | PT11 |
| P2.6 | SPI2_SS3 | CLCD_VSYNC |
| P2.7 | I2C0_SDA | — |
| P2.8 | I2C0_SCL | — |
| P2.9 | UART0_CTS | PT12 |
| P2.10 | UART0_RTS | PT14 |
| P2.11 | UART0_RX | PT13 |
| P2.12 | UART0_TX | PT15 |
| P2.13 | UART1_CTS | CLCD_R2 |
| P2.14 | UART1_RX | CLCD_R3 |
| P2.15 | UART1_RTS | CLCD_R4 |
| P2.16 | UART1_TX | CLCD_R5 |
| P2.17 | I2C1_SDA | CLCD_R6 |
| P2.18 | I2C1_SCL. This device pin also has a special function associated with the Secure Communications Protocol Bootloader. See Table 3 for details. | CLCD_R7. This device pin also has a special function associated with the Secure Communications Protocol Bootloader. See Table 3 for details. |
| P2.19* | — | — |
| P2.20* | — | — |
| P2.21* | — | — |
| P2.22* | — | — |
| P2.23 | PT6 | SPIXR_SDIO3** |
| P2.24* | — | — |
| P2.25 | PT11 | — |
| P2.26 | PT12 | — |
| P2.27* | — | — |
| P2.28 | PT14. This device pin also has a special function associated with the Secure Communications Protocol Bootloader. See Table 3 for details. | This device pin also has a special function associated with the Secure Communications Protocol Bootloader. See Table 3 for details. |
| P2.29* | — | — |
| P2.30 | PT1 | — |
| P2.31* | — | — |
| P3.0 | PDOWN†† | HYP_CS1N |
| P3.1 | SPI0_MISO | — |
| P3.2 | SPI0_MOSI | — |
| P3.3 | SPI0_SCK | — |
| P3.4 | TMR0 | — |
| P3.5 | TMR2 | — |
| P3.6 | TMR4 | — |
| P3.7 | TMR1 | — |
| P3.8 | TMR3 | — |
| P3.9 | TMR5 | — |
*GPIO not pinned out.
**This signal can be mapped to more than one GPIO, but there is only one instance of this peripheral.
†I2S_BCLK, I2S_LRCLK, I2S_SDI, I2S_SDO when enabled.
††PDOWN does not operate during or immediately after reset since this function appears as an Alternate Function 1.
†††Single-wire debug when enabled.